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Infineon XMC4500 ARM Cortex-M4F Demo
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See also the FAQ My application does not run, what could be wrong?
The IAR Embedded Workbench for ARM demo project workspace is called RTOSDemo.eww, and is located in the FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_IAR directory of the official FreeRTOS .zip file download.
The Keil uVision demo project is called RTOSDemo.uvproj, and is located in the FreeRTOS/Demo/CORTEX_M4F_Infineon_XMC4500_Keil directory of the official FreeRTOS .zip file download.
main_blinky() creates one queue, and two tasks. It then starts the RTOS scheduler.
The queue send task is implemented by the prvQueueSendTask() function in main_blinky.c. prvQueueSendTask() sits in a loop that causes it to repeatedly block for 200 milliseconds, before sending the value 100 to the queue that was created within main_blinky(). Once the value is sent, the task loops back around to block for another 200 milliseconds.
The queue receive task is implemented by the prvQueueReceiveTask() function in main_blinky.c. prvQueueReceiveTask() sits in a loop where it repeatedly blocks on attempts to read data from the queue that was created within main_blinky(). When data is received, the task checks the value of the data, and if the value equals the expected 100, toggles the LED. The 'block time' parameter passed to the queue receive function specifies that the task should be held in the Blocked state indefinitely to wait for data to be available on the queue. The queue receive task will only leave the Blocked state when the queue send task writes to the queue. As the queue send task writes to the queue every 200 milliseconds, the queue receive task leaves the Blocked state every 200 milliseconds, and therefore toggles the LED every 200 milliseconds.
This demo application demonstrates:
main() creates 43 tasks before starting the RTOS scheduler. The demo then dynamically and continuously creates and deletes a further two tasks while it is running.
Application specific "register test" tasks are created in addition to the standard demo tasks. These start by filling all the generic, and all the floating point registers, with known values. The tasks then repeatedly check that each register maintains the value written to it for the lifetime of the tasks. The register check tasks run at the idle priority, so will exit and re-enter the Running state frequently. The two register check tasks each fill the CPU registers with different values, and a register containing an unexpected value is symptomatic of an error in the context switching mechanism.
A 'check' software timer is created that periodically inspects the standard demo tasks, and register test tasks, to ensure all the tasks are functioning as expected. The check software timer's callback function toggles the single user LED on the XMC4500 Hexagon development kit CPU board. This gives a visual feedback of the system health. If the LED is toggling every 3 seconds, then the check software timer has not discovered any problems. If the LED is toggling every 200 milliseconds, then the check software timer has discovered a problem in one or more tasks.
This sets the frequency of the RTOS tick interrupt. The supplied value of 1000Hz is useful for testing the RTOS kernel functionality but is faster than most applications need. Lowering the frequency will improve efficiency.
See the RTOS kernel configuration documentation for full information on these configuration constants.
Whereas configKERNEL_INTERRUPT_PRIORITY and configMAX_SYSCALL_INTERRUPT_PRIORITY are full eight bit shifted values, defined to be used as raw numbers directly in the ARM Cortex-M4F NVIC registers, configLIBRARY_LOWEST_INTERRUPT_PRIORITY and configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY are equivalents that are defined using just the 6 priority bits implemented in the XMC4000 NVIC. These values are provided because the CMSIS library function NVIC_SetPriority() requires the unshifted 6 bit format.
Attention please!: See the page dedicated to setting interrupt priorities on ARM Cortex-M devices. Remember that ARM Cortex-M cores use numerically low priority numbers to represent HIGH priority interrupts. This can seem counter-intuitive and is easy to forget! If you wish to assign an interrupt a low priority do NOT assign it a priority of 0 (or other low numeric value) as this will result in the interrupt actually having the highest priority in the system - and therefore potentially make your system crash if this priority is above configMAX_SYSCALL_INTERRUPT_PRIORITY. Also, do not leave interrupt priorities unassigned, as by default they will have a priority of 0 and therefore the highest priority possible.
The lowest priority on a ARM Cortex-M core is in fact 255 - however different Cortex-M microcontroller manufacturers implement a different number of priority bits and supply library functions that expect priorities to be specified in different ways. For example, on Infineon XMC4000 ARM Cortex-M4 microcontrollers, the lowest priority you can specify is in fact 63 - this is defined by the constant configLIBRARY_LOWEST_INTERRUPT_PRIORITY in FreeRTOSConfig.h. The highest priority that can be assigned is always zero.
It is also recommended to ensure that all six priority bits are assigned as being preemption priority bits, and none as sub priority bits, as they are in the provided demo.
Each port #defines 'portBASE_TYPE' to equal the most efficient data type for that processor. This port defines portBASE_TYPE to be of type long.
Note that portEND_SWITCHING_ISR() will leave interrupts enabled.
The following source code snippet is provided as an example. The interrupt uses a semaphore to synchronise with a task (not shown), and calls portEND_SWITCHING_ISR to ensure the interrupt returns directly to the task.
void Dummy_IRQHandler(void)
{
long lHigherPriorityTaskWoken = pdFALSE;
/* Clear the interrupt if necessary. */
Dummy_ClearITPendingBit();
/* This interrupt does nothing more than demonstrate how to synchronise a
task with an interrupt. A semaphore is used for this purpose. Note
lHigherPriorityTaskWoken is initialised to zero. */
xSemaphoreGiveFromISR( xTestSemaphore, &lHigherPriorityTaskWoken );
/* If there was a task that was blocked on the semaphore, and giving the
semaphore caused the task to unblock, and the unblocked task has a priority
higher than the current Running state task (the task that this interrupt
interrupted), then lHigherPriorityTaskWoken will have been set to pdTRUE
internally within xSemaphoreGiveFromISR(). Passing pdTRUE into the
portEND_SWITCHING_ISR() macro will result in a context switch being pended to
ensure this interrupt returns directly to the unblocked, higher priority,
task. Passing pdFALSE into portEND_SWITCHING_ISR() has no effect. */
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
}
Only FreeRTOS API functions that end in "FromISR" can be called from an interrupt service routine - and then only if the priority of the interrupt is less than or equal to that set by the configMAX_SYSCALL_INTERRUPT_PRIORITY configuration constant (or configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY).