I’m using FreeRTOS hardly with MicroBlaze5 on the ML-401 board. Great Work !!! Thank you Richard Barry. Regarding to the FreeRTOS port for the MicroBlaze I feel free to recommend the following change: port.c line 53/54 /* Tasks are started with interrupts enabled. */ #define portINITIAL_MSR_STATE        ( ( portSTACK_TYPE ) 0x02 ) change to /* Tasks are started with interrupts enabled. */ #define portINITIAL_MSR_STATE        ( ( portSTACK_TYPE )  (XPAR_MICROBLAZE_0_RESET_MSR | 0x02) ) Background: You can (I do) use the MicroBlaze with instruction cache & data cache. The ICE/DCE bit (instruction/data cache enable bit) is contained inside the MSR (Machine Status Register). The ICE/DCE bit will be lost each time a task is created, because the MSR initial state in stack clears them. One way to avoid this is to use the initial state given in the define from the Xilinx EDK. Regards Dirk

Thanks for your valuable feedback.  I will open a change request with your suggestion. Regards.