Quality RTOS & Embedded Software

 Real time embedded FreeRTOS RSS feed 
Real time embedded FreeRTOS mailing list 
Quick Start Supported MCUs PDF Books Trace Tools Ecosystem TCP & FAT Training




Loading

Spurious Interrupts ond LPC

Posted by stefanvogel on August 13, 2008
Hi all.

In my project I loose interrupts from time to time. As I can see in the LPC214x usermanual the reason could be spurious interrupts. I would like to add those lines (according to NXP usermanual) at the beginning of portSAVE_CONTEXT() to aviod spurious interrupts:

__asm{ SUB LR, LR, #4 }; /* Spurious Interrupts: Adjust LR to point to return */ \
__asm{ STMFD SP!, {..., LR} }; /* Spurious Interrupts: Get some free regs */ \
__asm{ MRS LR, SPSR }; /* Spurious Interrupts: See if we got an interrupt while */ \
__asm{ TST LR, #0x80 }; /* Spurious Interrupts: interrupts were disabled. (I_Bit 0x80) */ \
__asm{ LDMNEFD SP!, {..., PC}^ }; /* Spurious Interrupts: If so, just return immediately.*/ \
/* Spurious Interrupts: The interrupt will remain pending since we haven’t */ \
/* Spurious Interrupts: acknowledged it and will be reissued when interrupts */ \
/* Spurious Interrupts: are next enabled. */ \
/* Spurious Interrupts: Rest of interrupt routine */ \

But then the controller ends in a data abort interrupt.

Any idea (I'm not very familiar with assembler)?

Thanks for your answer, kind regards stefan


RE: Spurious Interrupts ond LPC

Posted by Dave on August 13, 2008
This will definitely crash the code. Is there not a separate spurious interrupt handler that can be defined, or am I thinking of the SAM7?

RE: Spurious Interrupts ond LPC

Posted by stefanvogel on August 14, 2008
There is a default interrupt handler and I set it up. But I'm still loosing some interrupts without getting into this routine (I set a breakpoint in it). So it seems that the default interrupt handler doesn't solve all problems with spurious interrupts.

RE: Spurious Interrupts ond LPC

Posted by David Farrell on August 20, 2008
It looked like I was loosing interrupts by using level triggered
interrupts for the task tick. I switched to edge and things ran
much better. Review my thread on this.
David.

RE: Spurious Interrupts ond LPC

Posted by stefanvogel on September 10, 2008
No, im not using level triggered interrupts. I'm already using edge interrupts.

I added a function vtogglePIN() to vPortEnterCritical() and vPortExitCritical() which toggles an output port. Now i can see that in some cases my interrupts are disabled for about 20ms. This is a strange behaviour and i don't know really why this ist happening. In my application im waiting for an semaphore which is given by an ISR from an externel Interrupt. Normally I'm just yielded while waiting for this interrupt. But sometimes I'm yielded with interrupts disabled (vPortEnterCritical entered and vPortExitCritical not yet called). In my code I commented all vPortEnterCritical() out, so this must be generated by freeRTOS itself.

Any idea?

RE: Spurious Interrupts ond LPC

Posted by Richard on September 10, 2008
> I added a function vtogglePIN() to vPortEnterCritical() and
> vPortExitCritical() which toggles an output port. Now i can
> see that in some cases my interrupts are disabled for about
> 20ms. This is a strange behaviour and i don't know really why
> this ist happening. In my application im waiting for an
> semaphore which is given by an ISR from an externel
> Interrupt. Normally I'm just yielded while waiting for this
> interrupt. But sometimes I'm yielded with interrupts disabled

In the existing ARM7 port each task maintains its own interrupt status. The scheduler will yield from within a critical section but this does not mean that interrupt remain disabled until the task runs again - if that were the case then everything would just come to a halt immediately. When a task yields from within a critical section it can yield to a task that has interrupts enabled, so adding a pin toggle in the enter/exit critical macros does not show you how long interrupts are being disabled for. When the original task runs again it will resume from within the critical section so will start with interrupts disabled. This is how that particular port is intended to work. More recent ports use a different scheme.

Regards.


[ Back to the top ]    [ About FreeRTOS ]    [ Sitemap ]    [ ]




Copyright (C) 2004-2010 Richard Barry. Copyright (C) 2010-2016 Real Time Engineers Ltd.
Any and all data, files, source code, html content and documentation included in the FreeRTOSTM distribution or available on this site are the exclusive property of Real Time Engineers Ltd.. See the files license.txt (included in the distribution) and this copyright notice for more information. FreeRTOSTM and FreeRTOS.orgTM are trade marks of Real Time Engineers Ltd.

Latest News:

FreeRTOS V9.0.0 is now available for download.


Free TCP/IP and file system demos for the RTOS


Sponsored Links

⇓ Now With No Code Size Limit! ⇓
⇑ Free Download Without Registering ⇑


FreeRTOS Partners

ARM Connected RTOS partner for all ARM microcontroller cores

Renesas Electronics Gold Alliance RTOS Partner.jpg

Microchip Premier RTOS Partner

RTOS partner of NXP for all NXP ARM microcontrollers

Atmel RTOS partner supporting ARM Cortex-M3 and AVR32 microcontrollers

STMicro RTOS partner supporting ARM7, ARM Cortex-M3, ARM Cortex-M4 and ARM Cortex-M0

Xilinx Microblaze and Zynq partner

Silicon Labs low power RTOS partner

Altera RTOS partner for Nios II and Cortex-A9 SoC

Freescale Alliance RTOS Member supporting ARM and ColdFire microcontrollers

Infineon ARM Cortex-M microcontrollers

Texas Instruments MCU Developer Network RTOS partner for ARM and MSP430 microcontrollers

Cypress RTOS partner supporting ARM Cortex-M3

Fujitsu RTOS partner supporting ARM Cortex-M3 and FM3

Microsemi (previously Actel) RTOS partner supporting ARM Cortex-M3

Atollic Partner

IAR Partner

Keil ARM Partner

Embedded Artists