Quality RTOS & Embedded Software

 Real time embedded FreeRTOS RSS feed 
Real time embedded FreeRTOS mailing list 
Quick Start Supported MCUs PDF Books Trace Tools Ecosystem TCP & FAT Training




Loading

Code size issue

Posted by Subhash on December 9, 2011
Hi,

I am developing software for the STR912FAW44 using the IAR Embedded Workbench version 5.50.5. I am facing a problem when the code size exceeds about 64K. The code does not execute from the flash. The same code works when I debug it using a the J-Link debugger. But when I download it using the J-Link debugger it doesn’t work. I tried both the builds i.e. debug and release. The only difference between these 2 is that the “DEBUG” is defined in the debug build and NOT in the release build.

I have set the bank 0 as a boot bank and don’t have a boot loader. I believe the debugger downloads the code to the bank 0. The bank 0 address is set as 0x0000. If I comment out some code it works. I observed the code size ( Code and Read only data) in the map file and observed that the code doesn’t work if the size exceeds about 64K. The STR912FAW44 has 512K bytes of flash in the bank 0 and it’s divided into 8 sectors. Each sector is 64K. I have different licensed dongles and tried with them .
Is there any issue in downloading the code or building it if the code size crosses the first sector boundary?

I use the FreeRTOS ver 7.0.1 and use the initialization files 91x_init.s and 91x_vect.s come with that. I use the heap_2.c implementation from the FreeRTOS for heap. It allocates the heap as a fixed size array. Also, I have 2 projects:
1.FreeRTOS project is built as a library using “C” complier and
2.The application project built as an executable with the “Embedded C++” compiler option.

The Flash memory configuration used is:
FMI_BankRemapConfig(4, 2, 0, 0x80000 ); /* FMI_BootBankSize, FMI_NonBootBankSize, FMI_BootBankAddress, FMI_NonBootBankAddress */
FMI_Config( FMI_READ_WAIT_STATE_2, FMI_WRITE_WAIT_STATE_0, FMI_PWD_ENABLE, FMI_LVD_ENABLE, FMI_FREQ_HIGH );

Thanks for the help you provide.

RE: Code size issue

Posted by Richard Damon on December 10, 2011
One thing I remember having a problem with this part was you need to make sure the startup file loads low enough in memory, the flash register power up with a predefined amount of flash, which is much smaller than you actually have, and if the start-up code is outside that, then the CPU will address-error when accessing memory outside that initial bound until the startup adjusts those registers. If you run under the debugger, the debugging executive will have done this automatically, so it won't have caused the problem.

RE: Code size issue

Posted by Richard on December 10, 2011
Sorry, I can't help you with the technical specifics of the chip boot process or memory lay out. I thought maybe the vector table was using direct branches to the interrupt handler functions, and the when the code size grew too large, the branch distance was too far away. However, having looked at the files you reference, that is not the case as indirect 32 bit branches are used, which will always be fine.

Regards.

RE: Code size issue

Posted by Subhash on December 12, 2011
Hi Richard,

Thanks for the response. It looks like that is the case. I was looking into the map file to check the code size. The part of the code that exceeds the 64KB boundry is:
Section Kind Address Size Object
Initializer bytes ro data 0x00009706 0x75fe
- 0x00010d04 0x10b6c

So the initializer bytes are crossing the boundry. How do I force the linker to place it in the lower memory area?

Thanks

RE: Code size issue

Posted by Richard Damon on December 13, 2011
What I did was to edit the linker control file and defined a new region of memory for initialization code, that was limited to the bottom 16k of memory, and placed the startup module into that region.

RE: Code size issue

Posted by Subhash on December 13, 2011
Richard,

The linker file fix worked for me, although I did it differently. I just made the STR9 init module as the first module to be put in the ROM, after the interrupt vector.

Thank you very much; this was a great help.


[ Back to the top ]    [ About FreeRTOS ]    [ Sitemap ]    [ ]




Copyright (C) 2004-2010 Richard Barry. Copyright (C) 2010-2016 Real Time Engineers Ltd.
Any and all data, files, source code, html content and documentation included in the FreeRTOSTM distribution or available on this site are the exclusive property of Real Time Engineers Ltd.. See the files license.txt (included in the distribution) and this copyright notice for more information. FreeRTOSTM and FreeRTOS.orgTM are trade marks of Real Time Engineers Ltd.

Latest News:

FreeRTOS V9.0.0 is now available for download.


Free TCP/IP and file system demos for the RTOS


Sponsored Links

⇓ Now With No Code Size Limit! ⇓
⇑ Free Download Without Registering ⇑


FreeRTOS Partners

ARM Connected RTOS partner for all ARM microcontroller cores

Renesas Electronics Gold Alliance RTOS Partner.jpg

Microchip Premier RTOS Partner

RTOS partner of NXP for all NXP ARM microcontrollers

Atmel RTOS partner supporting ARM Cortex-M3 and AVR32 microcontrollers

STMicro RTOS partner supporting ARM7, ARM Cortex-M3, ARM Cortex-M4 and ARM Cortex-M0

Xilinx Microblaze and Zynq partner

Silicon Labs low power RTOS partner

Altera RTOS partner for Nios II and Cortex-A9 SoC

Freescale Alliance RTOS Member supporting ARM and ColdFire microcontrollers

Infineon ARM Cortex-M microcontrollers

Texas Instruments MCU Developer Network RTOS partner for ARM and MSP430 microcontrollers

Cypress RTOS partner supporting ARM Cortex-M3

Fujitsu RTOS partner supporting ARM Cortex-M3 and FM3

Microsemi (previously Actel) RTOS partner supporting ARM Cortex-M3

Atollic Partner

IAR Partner

Keil ARM Partner

Embedded Artists