Quality RTOS & Embedded Software

 Real time embedded FreeRTOS RSS feed 
Real time embedded FreeRTOS mailing list 
Quick Start Supported MCUs PDF Books Trace Tools Ecosystem TCP & FAT Training




Loading

PIC18 ISR Stack and HW stack

Posted by paul on July 27, 2012
The PIC18 does have a HW stack of 31 but can also be changed into a SW stack and this is what FreeRTOS is doing I can see from the code. But my question is what does FreeRTOS do if an interrupt happens does it save all variables of the interrupt on a special SW stack or simply on the interrupted task SW stack or maybe uses the HW stack ?.

Who knows ??..

paul.

RE: PIC18 ISR Stack and HW stack

Posted by Richard on July 27, 2012
There are several reasons why the PIC18 architecture, as per that used to generate the PIC18 port, is less than ideal to run a preemptive RTOS. The hardware stack is one, the banking another, and the compiler using RAM for temporaries yet another, still....

When an interrupt occurs the low interrupt runs, which calls a peripheral specific interrupt handler. So far, that is all done by the compiler generated code. If the peripheral interrupt then decides a context switch is required, the stacks are saved onto the task stack (including the memory area used by the compiler).

Regards.

RE: PIC18 ISR Stack and HW stack

Posted by paul on July 27, 2012
I know PIC18 is not ideal but the HW stack is not used but a SW stack is implemented by FreeRTOS solving this problem. My question was if the compiler memory area uded by the compiler is stored on a special stack like with PIC32 or on the task stack and why this is different !. It would be better to use the HW stack memory for this since its waisted now.

RE: PIC18 ISR Stack and HW stack

Posted by Richard on July 27, 2012
The PIC32 benefits greatly by implementing (in software) a separate system stack. This is for a few reasons: It has a lot of registers, the compilers ABI is very RAM hungry, and the PIC32 port has a full interrupt nesting model meaning the interrupt stack can get very deep. The PIC18 on the other hand is a massively more simple device, and does not support interrupt nesting - the stack never holds more than one interrupt stack frame and that is insignificant in size compared to the stack required to hold the context during a context switch.

Regards.


[ Back to the top ]    [ About FreeRTOS ]    [ Sitemap ]    [ ]




Copyright (C) 2004-2010 Richard Barry. Copyright (C) 2010-2016 Real Time Engineers Ltd.
Any and all data, files, source code, html content and documentation included in the FreeRTOSTM distribution or available on this site are the exclusive property of Real Time Engineers Ltd.. See the files license.txt (included in the distribution) and this copyright notice for more information. FreeRTOSTM and FreeRTOS.orgTM are trade marks of Real Time Engineers Ltd.

Latest News:

FreeRTOS V9.0.0 is now available for download.


Free TCP/IP and file system demos for the RTOS


Sponsored Links

⇓ Now With No Code Size Limit! ⇓
⇑ Free Download Without Registering ⇑


FreeRTOS Partners

ARM Connected RTOS partner for all ARM microcontroller cores

Renesas Electronics Gold Alliance RTOS Partner.jpg

Microchip Premier RTOS Partner

RTOS partner of NXP for all NXP ARM microcontrollers

Atmel RTOS partner supporting ARM Cortex-M3 and AVR32 microcontrollers

STMicro RTOS partner supporting ARM7, ARM Cortex-M3, ARM Cortex-M4 and ARM Cortex-M0

Xilinx Microblaze and Zynq partner

Silicon Labs low power RTOS partner

Altera RTOS partner for Nios II and Cortex-A9 SoC

Freescale Alliance RTOS Member supporting ARM and ColdFire microcontrollers

Infineon ARM Cortex-M microcontrollers

Texas Instruments MCU Developer Network RTOS partner for ARM and MSP430 microcontrollers

Cypress RTOS partner supporting ARM Cortex-M3

Fujitsu RTOS partner supporting ARM Cortex-M3 and FM3

Microsemi (previously Actel) RTOS partner supporting ARM Cortex-M3

Atollic Partner

IAR Partner

Keil ARM Partner

Embedded Artists