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FreeRTOS support for Freescale i.MX Solo X

Posted by waynera on July 9, 2015

To whom it may concern, I am interested in learning if FreeRTOS has a port to the Freescale i.MX6 Solo X SABRE-SD platform for either of the cores (A9 and M4). I do not see this listed on your supported platforms listing but am hoping you have support (CPU core + BSP) for this platform. We are in the beginning stages of a new product development and are interesting in using your RTOS. Please respond at your earliest convenience.


FreeRTOS support for Freescale i.MX Solo X

Posted by rtel on July 9, 2015

Although there is no official demo in the FreeRTOS download, we have been running FreeRTOS on the M4 core of the i.MX Solo part (on a Sabre board). FreeRTOS will actually run on any Cortex-M core without any porting being required. This is because the kernel is not dependent on any hardware outside of the Cortex-M core itself (the clock and interrupt controller are built into the core).

Do you have a bare metal application running on the hardware already? If so you should be able to add in the FreeRTOS source files, and install the FreeRTOS PendSV, SysTick and SVCCall interrupt, and be running. http://www.freertos.org/Creating-a-new-FreeRTOS-project.html

Items to watch out for are the configPRIOBITS and configMAXSYSCALLINTERRUPTPRIORITY settings. I've just checked our i.MX Solo project and find the following - which may or may not be correct ;o)

[more info below the code snippet]

/* Cortex-M specific definitions. */
#ifdef __NVIC_PRIO_BITS
	/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
	#define configPRIO_BITS       		__NVIC_PRIO_BITS
#else
	#define configPRIO_BITS       		4        /* 15 priority levels */
#endif

/* The lowest interrupt priority that can be used in a call to a "set priority"
function. */
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY			0xf

/* The highest interrupt priority that can be used by any interrupt service
routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY	5

/* Interrupt priorities used by the kernel port layer itself.  These are generic
to all Cortex-M ports, and do not rely on any particular library functions. */
#define configKERNEL_INTERRUPT_PRIORITY 		( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )

/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )

If the Cortex-A9 core is using a standard ARM GIC (Generic Interrupt Controller) then FreeRTOS will also run on that without modification, provided you set the base addresses for the GIC correctly. Sometimes FreeRTOS will use their own IP for things like the interrupt controller, and MPU, etc. If that is the case on this part then some porting work will be required. I'm afraid I've never looked at the A9 core on this specific chip.

As I recall, and my memory might be wrong, we used GCC to build the code, ARM DS-5 to download and debug the code, and a D-Stream as the debugging interface. The M4 core must be clocked and enabled by the A9 core, but this can be done by peeking and poking the necessary registers using a debugger script - allowing you to develop on the M core without the A core running at all. It won't boot like that though, to boot you need something actually running on the A core to problematically start the M core then load the excitable binary image.

Regards.


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