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Non Tickless Idle low power state

Posted by richarddamon on July 10, 2017

Many processors have an instruction like the Arm WFI (Wait for Interrupt) that is basically a free reduce power instruction. It doesn't save as much power as the sort of thing used in tickless idle, but doesn't have some of the issues of the deeper sleep, since the clocks keep running at a global state, it just stops the processor, and thus reduces the power draw of the processor.

Typically, I have implemented using this instruction via the IdleHook, having it execute the WFI like instruction. When looking at implementing a Tickless Idle mode, I realize that this has the issue of possibly delaying, and perhaps preventing, the entry into Tickless Idle, as the Idle Hook is called unconditionally (if enabled) jus before testing if we can enter Tickless Idle, so the WFI will delay till the next tick. Totally omitting the instruction may raise power draw as it we are going to do something in a tick or two, tickless idle will be blocked, while this would seem to be a good opertunity to use something like WFI.

What would seem useful would be for the port layer to optionally define such a lower power mode, similar to the way it defines an entry to tickless idle, and then add code to the idle task to call this in the following conditions:

1) configIDLESHOULDYIELD == 0, if it isn't then the user may have their own idle level task that can use the processor tine. 2) Either tickless idle is not enabled, or the tickless idle code has determined the processor will be needed too soon to be worth going into tickless idle.

Does this make sense as an idea for a feature request? Figured worth discussion before making a formal featuure request, or perhaps I missed another way to do this already.

Non Tickless Idle low power state

Posted by rtel on July 10, 2017

Yes, please add a feature request ticket in SourceForge.

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