Quality RTOS & Embedded Software

 Real time embedded FreeRTOS RSS feed 
Real time embedded FreeRTOS mailing list 
Quick Start Supported MCUs PDF Books Trace Tools Ecosystem TCP & FAT Training




Loading

how to support interrupt nested in cpu without NVIC

Posted by zhuchunxia on June 21, 2016

Hi: in my port source file. my interrupt porting code like this define portDISABLEINTERRUPTS() vPortDisableInterrupt() define portENABLEINTERRUPTS() vPortEnableInterrupt() define portSETINTERRUPTMASKFROMISR() GetLocalPSR() define portCLEARINTERRUPTMASKFROMISR(x) SetLocalPSR(x)

GetLocalPSR() will return current interrupt enable flag and disable interrupt SetLocalPSR(x) will store interrupt enable flag by x.

it seems to not support interrupt nested as portSETINTERRUPTMASKFROMISR() disable all interrupt.

should I set mask to those interrupts which is lower than current interrrupt priority to allow higher priority interrupt happen ?

vincent


how to support interrupt nested in cpu without NVIC

Posted by rtel on June 21, 2016

If you are implementing a full interrupt nesting scheme then both taskENTERCRITICAL() and taskENTERCRITICALFROMISR() [also called portSETINTERRUPTMASKFROMISR()] should disable interrupts up to a user defined maximum interrupt priority. The interrupts that have a priority above that maximum will never be disabled by the RTOS, but cannot use the FreeRTOS API.

If you are in a critical section then you don't want interrupts below the user defined maximum to be able to execute - this is not related to interrupt nesting as such as interrupts at or below the above mentioned user defined maximum priority can only nest when you are outside of a critical section (which is the point of entering the critical section).


how to support interrupt nested in cpu without NVIC

Posted by zhuchunxia on June 22, 2016

the user defined maximum interrupt priority you mentioned is configMAXSYSCALLINTERRUPT_PRIORITY ? I know the value is used to set interrupt priority register instead of RTOS kernel . my cpu has no interrupt priority register to rearrange all interrupt prority.


[ Back to the top ]    [ About FreeRTOS ]    [ Sitemap ]    [ ]




Copyright (C) 2004-2010 Richard Barry. Copyright (C) 2010-2016 Real Time Engineers Ltd.
Any and all data, files, source code, html content and documentation included in the FreeRTOSTM distribution or available on this site are the exclusive property of Real Time Engineers Ltd.. See the files license.txt (included in the distribution) and this copyright notice for more information. FreeRTOSTM and FreeRTOS.orgTM are trade marks of Real Time Engineers Ltd.

Latest News:

FreeRTOS V9.0.0 is now available for download.


Free TCP/IP and file system demos for the RTOS


Sponsored Links

⇓ Now With No Code Size Limit! ⇓
⇑ Free Download Without Registering ⇑


FreeRTOS Partners

ARM Connected RTOS partner for all ARM microcontroller cores

Renesas Electronics Gold Alliance RTOS Partner.jpg

Microchip Premier RTOS Partner

RTOS partner of NXP for all NXP ARM microcontrollers

Atmel RTOS partner supporting ARM Cortex-M3 and AVR32 microcontrollers

STMicro RTOS partner supporting ARM7, ARM Cortex-M3, ARM Cortex-M4 and ARM Cortex-M0

Xilinx Microblaze and Zynq partner

Silicon Labs low power RTOS partner

Altera RTOS partner for Nios II and Cortex-A9 SoC

Freescale Alliance RTOS Member supporting ARM and ColdFire microcontrollers

Infineon ARM Cortex-M microcontrollers

Texas Instruments MCU Developer Network RTOS partner for ARM and MSP430 microcontrollers

Cypress RTOS partner supporting ARM Cortex-M3

Fujitsu RTOS partner supporting ARM Cortex-M3 and FM3

Microsemi (previously Actel) RTOS partner supporting ARM Cortex-M3

Atollic Partner

IAR Partner

Keil ARM Partner

Embedded Artists