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xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 16, 2016

Hi, I have been working around with a mechanism with in tiva tm4c1294 micrcontroller, where two ADCs will periodically send interrupts and the the interrrupt isrs will post task notifications to an ADC process task, where the task is waiting with xtasknotifywait api. My issue is I could see the task getting triggered from the isr, the task notification value in the tcb structure of the task getting changed accordingly. But my task is not getting unblocked. Here is my adc code:

/*
 * ADC_Config.c
 *
 *  Created on: Mar 13, 2016
 *      Author: index
 */
#include 
#include 
#include "inc/hw_gpio.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/gpio.h"
#include "driverlib/pin_map.h"
#include "driverlib/rom.h"
#include "driverlib/rom_map.h"
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "semphr.h"
#include "driverlib/sysctl.h"
#include "drivers/pinout.h"
#include "driverlib/adc.h"
#include "ADC_Config.h"

void ADCConfig(void)
{
	MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
	MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_ADC0);

	MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
	MAP_SysCtlPeripheralReset(SYSCTL_PERIPH_ADC1);

	//
	// Configure the ADC to use PLL at 480 MHz divided by 16 to get an ADC
	// clock of 30 MHz.
	//
	ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 16);//ADC0 and ADC1 are configured with ADC0 itself

	ADCIntRegister(ADC0_BASE, SEQ0,ADC0_INT_Handler);
	ADCIntRegister(ADC1_BASE, SEQ0,ADC1_INT_Handler);

    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);//AIN3-AIN2(PE3-PE2), AIN1-AIN0(PE1-PE0), differential mode
	MAP_GPIOPinTypeADC(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 );

    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);//AIN4(PD3) ,AIN12(PD7)
    MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_3 | GPIO_PIN_7);

    MAP_ADCSequenceDisable(ADC0_BASE, SEQ0);
    MAP_ADCSequenceDisable(ADC0_BASE, SEQ1);
    MAP_ADCSequenceDisable(ADC0_BASE, SEQ2);
    MAP_ADCSequenceDisable(ADC0_BASE, SEQ3);//All sequencers disabled.
    MAP_ADCSequenceConfigure(ADC0_BASE, SEQ0, ADC_TRIGGER_PROCESSOR, PriorityVeryHigh);

    //Technique to get simultaneous sampling from sequential sampling, Avg corresponding results, you get the simultaneously sampled result.
    MAP_ADCSequenceStepConfigure(ADC0_BASE,SEQ0, 0, ADC_CTL_SHOLD_256 | ADC_CTL_D|ADC_CTL_CH0);//VoltageSense
    MAP_ADCSequenceStepConfigure(ADC0_BASE,SEQ0, 1, ADC_CTL_SHOLD_256 | ADC_CTL_D|ADC_CTL_CH1);//CurrentSense
    MAP_ADCSequenceStepConfigure(ADC0_BASE,SEQ0, 2, ADC_CTL_SHOLD_256 | ADC_CTL_D|ADC_CTL_CH1);//CurrentSense
    MAP_ADCSequenceStepConfigure(ADC0_BASE,SEQ0, 3, ADC_CTL_SHOLD_256 | ADC_CTL_D|ADC_CTL_CH0);//VoltageSense
    MAP_ADCSequenceStepConfigure(ADC0_BASE,SEQ0, 4, ADC_CTL_SHOLD_256 | ADC_CTL_D|ADC_CTL_CH0);//VoltageSense
    MAP_ADCSequenceStepConfigure(ADC0_BASE,SEQ0, 5, ADC_CTL_SHOLD_256 | ADC_CTL_D|ADC_CTL_CH1);//CurrentSense
    MAP_ADCSequenceStepConfigure(ADC0_BASE,SEQ0, 6, ADC_CTL_SHOLD_256 | ADC_CTL_D|ADC_CTL_CH1);//CurrentSense
    MAP_ADCSequenceStepConfigure(ADC0_BASE,SEQ0, 7, ADC_CTL_SHOLD_256 | ADC_CTL_D|ADC_CTL_CH0| ADC_CTL_IE |ADC_CTL_END);//VoltageSense, Ending the sequence\

    MAP_ADCSequenceDisable(ADC1_BASE, SEQ0);
    MAP_ADCSequenceDisable(ADC1_BASE, SEQ1);
    MAP_ADCSequenceDisable(ADC1_BASE, SEQ2);
    MAP_ADCSequenceDisable(ADC1_BASE, SEQ3);//All sequencers disabled.
    MAP_ADCSequenceConfigure(ADC1_BASE, SEQ0, ADC_TRIGGER_PROCESSOR, PriorityVeryHigh);

    MAP_ADCSequenceStepConfigure(ADC1_BASE,SEQ0, 0, ADC_CTL_SHOLD_256 | ADC_CTL_CH12);//DCVoltageSense
    MAP_ADCSequenceStepConfigure(ADC1_BASE,SEQ0, 1, ADC_CTL_SHOLD_256 | ADC_CTL_CH4);//DCCurrentSense
    MAP_ADCSequenceStepConfigure(ADC1_BASE,SEQ0, 2, ADC_CTL_SHOLD_256 | ADC_CTL_CH12);//DCVoltageSense
    MAP_ADCSequenceStepConfigure(ADC1_BASE,SEQ0, 3, ADC_CTL_SHOLD_256 | ADC_CTL_CH4);//DCCurrentSense
    MAP_ADCSequenceStepConfigure(ADC1_BASE,SEQ0, 4, ADC_CTL_SHOLD_256 | ADC_CTL_CH12);//DCVoltageSense
    MAP_ADCSequenceStepConfigure(ADC1_BASE,SEQ0, 5, ADC_CTL_SHOLD_256 | ADC_CTL_CH4);//DCCurrentSense
    MAP_ADCSequenceStepConfigure(ADC1_BASE,SEQ0, 6, ADC_CTL_SHOLD_256 | ADC_CTL_TS);//Temperature Sensor
    MAP_ADCSequenceStepConfigure(ADC1_BASE,SEQ0, 7, ADC_CTL_SHOLD_256 | ADC_CTL_TS| ADC_CTL_END | ADC_CTL_IE);//Temperature Sensor, Ending the sequence

    MAP_ADCSequenceEnable(ADC0_BASE, SEQ0);//sequencers are enabled
    MAP_ADCSequenceEnable(ADC1_BASE, SEQ0);

    //MAP_ADCIntEnable(ADC0_BASE, SEQ0);
    //MAP_ADCIntEnable(ADC1_BASE, SEQ0);
}

uint32_t uiDataBuffer0[8];
uint32_t uiDataCount0,uiADC0_Misalign = 0,ADC0_Counter=0;

extern xTaskHandle xADC_DataProcessTaskHandle;
#define ADC0_Notification	(0x01)
#define ADC1_Notification	(0x02)

void ADC0_INT_Handler(void)
{
	portBASE_TYPE pxHigherPriorityTaskWoken = pdFALSE;
	ADCIntClear(ADC0_BASE, SEQ0);
	ADC0_Counter++;
	xTaskNotifyFromISR(xADC_DataProcessTaskHandle, (uint32_t)ADC0_Notification, eSetBits, &pxHigherPriorityTaskWoken);
	portYIELD_FROM_ISR(pxHigherPriorityTaskWoken);
}

uint32_t uiDataBuffer1[8];
uint32_t uiDataCount1,uiADC1_Misalign=0,ADC1_Counter=0;

void ADC1_INT_Handler(void)
{
	portBASE_TYPE pxHigherPriorityTaskWoken =pdFALSE;
	ADCIntClear(ADC1_BASE, SEQ0);
	ADC1_Counter++;
	xTaskNotifyFromISR(xADC_DataProcessTaskHandle, (uint32_t)ADC1_Notification, eSetBits, &pxHigherPriorityTaskWoken);
	portYIELD_FROM_ISR(pxHigherPriorityTaskWoken);
}

float fDieTemperature = 0.0;
uint32_t ADC_DataProcessTaskEntryCounter=0;

void ADC_DataProcessTask(void * pvParamerters)
{
	uint32_t ui32NotifiedValue;
	for( ; ; )
	{
		xTaskNotifyWait(pdFALSE, ULONG_MAX, &ui32NotifiedValue, portMAX_DELAY);
		fDieTemperature+=1.0;
		ADC_DataProcessTaskEntryCounter++;
		if( (ui32NotifiedValue & ADC0_Notification) != 0)
		{
			uiDataCount0 = ADCSequenceDataGet(ADC0_BASE, SEQ0, uiDataBuffer0);
			if(uiDataCount0 != 8) uiADC0_Misalign++;
		}
		else if( (ui32NotifiedValue & ADC1_Notification) != 0)
		{
			uiDataCount1 = ADCSequenceDataGet(ADC1_BASE, SEQ0, uiDataBuffer1);
			if(uiDataCount1 != 8) uiADC1_Misalign++;
		}
	}
}

First function is my ADC init.
ADC0,ADC1 interrupt handlers are seen as second and third functions and last one is my task.
Interrupts are found to be working fine.

task is created in the main function like this.

int
main(void)
{
    //
    // Configure the system frequency.
    //
    g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
                                             SYSCTL_OSC_MAIN |
                                             SYSCTL_USE_PLL |
                                             SYSCTL_CFG_VCO_480), 120000000);

    //
    // Configure the device pins for this board.
    // This application uses Ethernet but not USB.
    //
    //PinoutSet(true, false);

    ButtonsInit();
    SPI3Config();
    ADCConfig();
    PWMConfig();

    if(xTaskCreate(SSI_DAC_Task, (const portCHAR *)"SSI_DAC_Task   ", SSI_DAC_TASK_STACK_SIZE, NULL, tskIDLE_PRIORITY +
			PRIORITY_SSI_DAC_TASK, &xSSI_DAC_TaskHandle) != pdTRUE)
    	exit(1);

    if(xTaskCreate(ADC_DataProcessTask, (const portCHAR *)"ADC_ProcssTsk  ", ADC_DataProcessTask_STACK_SIZE, NULL, tskIDLE_PRIORITY +
			PRIORITY_ADC_DataProcessTask, &xADC_DataProcessTaskHandle) != pdTRUE)
    	exit(1);

    if(xTaskCreate(MasterControlTask, (const portCHAR *)"MasterCtlTsk   ", MasterControlTask_STACK_SIZE, NULL, tskIDLE_PRIORITY +
			PRIORITY_MasterControlTask, &xMasterControlTaskHandle) != pdTRUE)
    	exit(1);


	//
	// Start the scheduler.  This should not return.
	//
	vTaskStartScheduler();

    while(1);
    
What could be wrong?
Is there any problem with task notify apis?

regards
Sijomon

xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by rtel on March 16, 2016

What are you setting the priority of the interrupts to? It must be below configMAXSYSCALLINTERRUPT_PRIORITY. If you are using a relatively new version of FreeRTOS and have configASSERT() defined then you will hit an assertion failure if the priority is wrong.


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 16, 2016

/* Be ENORMOUSLY careful if you want to modify these two values and make sure * you read http://www.freertos.org/a00110.html#kernel_priority first! */

define configKERNELINTERRUPTPRIORITY ( 7 << 5 )

/* Priority 7, or 0xE0 as only the top three bits are implemented. This is the lowest priority. */

define configMAXSYSCALLINTERRUPT_PRIORITY ( 5 << 5 )

/* Priority 5, or 0xA0 as only the top three bits are implemented. */

Are these right? regards, Sijomon


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 16, 2016

I have not changed the freertosconfig.h from the new version downloaded yesterday. This was available with an example iot program coming with tivaware package provided by TI. sijomon


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 16, 2016

~~~~ /* FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.

***************************************************************************
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 *    professional grade, cross platform, de facto standard solutions    *
 *    for microcontrollers - completely free of charge!                  *
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 *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *
 *                                                                       *
 *    Thank you for using FreeRTOS, and thank you for your support!      *
 *                                                                       *
***************************************************************************


This file is part of the FreeRTOS distribution.

FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel.  FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.

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http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.

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critical systems.

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*/

ifndef FREERTOSCONFIGH
define FREERTOSCONFIGH

/----------------------------------------------------------- * Application specific definitions. * * These definitions should be adjusted for your particular hardware and * application requirements. * * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. * * See http://www.freertos.org/a00110.html. *----------------------------------------------------------/

define configUSE_PREEMPTION 1
define configUSEIDLEHOOK 0
define configUSETICKHOOK 0
define configCPUCLOCKHZ ( ( unsigned long ) 120000000 )
define configTICKRATEHZ ( ( portTickType ) 1000 )
define configMINIMALSTACKSIZE ( ( unsigned short ) 200 )
define configTOTALHEAPSIZE ( ( size_t ) ( 65535 ) )
define configMAXTASKNAME_LEN ( 15 )
define configUSETRACEFACILITY 1
define configUSE16BIT_TICKS 0
define configIDLESHOULDYIELD 0
define configUSECOROUTINES 0
define configUSE_MUTEXES 1
define configUSERECURSIVEMUTEXES 0
define configCHECKFORSTACK_OVERFLOW 2
define configUSE_TIMERS 0
define configTIMERTASKPRIORITY 6
define configTIMERQUEUELENGTH 5
define configTIMERTASKSTACK_DEPTH 256
define configUSEPORTOPTIMISEDTASKSELECTION 1
define configUSETASKNOTIFICATIONS 1

// // Configure the FreeRTOS utils to generate run time stats for each task. // This is primarily not a production intent feature of FreeRTOS. But is very // useful and educational and interesting for purpose of this eval kit app. // http://www.freertos.org/rtos-run-time-stats.html // // The app must create a timer (generally hardware) that will update this // counter variable at a constant rate at least 10 times faster than the tick // rate. See Timer0IntHandler function in senshub_iot.c for this apps timer // implementation. //

ifndef IARSYSTEMSASM

extern volatile unsigned long g_vulRunTimeStatsCountValue;

endif
define configGENERATERUNTIME_STATS 1
define portCONFIGURETIMERFORRUNTIME_STATS()
                                        g_vulRunTimeStatsCountValue = 0ul
define portGETRUNTIMECOUNTERVALUE() g_vulRunTimeStatsCountValue
define configMAXPRIORITIES ( ( unsigned portBASETYPE ) 16 )
define configMAXCOROUTINE_PRIORITIES ( 2 )
define configQUEUEREGISTRYSIZE 10

/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */

define INCLUDE_vTaskPrioritySet 1
define INCLUDE_uxTaskPriorityGet 1
define INCLUDE_vTaskDelete 1
define INCLUDE_vTaskCleanUpResources 1
define INCLUDE_vTaskSuspend 1
define INCLUDE_vTaskDelayUntil 1
define INCLUDE_vTaskDelay 1
define INCLUDE_uxTaskGetStackHighWaterMark 1

/* Be ENORMOUSLY careful if you want to modify these two values and make sure * you read http://www.freertos.org/a00110.html#kernel_priority first! */

define configKERNELINTERRUPTPRIORITY ( 7 << 5 )

/* Priority 7, or 0xE0 as only the top three bits are implemented. This is the lowest priority. */

define configMAXSYSCALLINTERRUPT_PRIORITY ( 5 << 5 )

/* Priority 5, or 0xA0 as only the top three bits are implemented. */

endif /* FREERTOSCONFIGH */

~~~~ This is the config file I use. Any issues? sijomon


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by rtel on March 16, 2016

Are these right?

If the Tiva has 3 priority bits then they look correct - but you also need to ensure the priority actually set in the peripheral is correct too.

I have not changed the freertosconfig.h from the new version downloaded yesterday.

....and is that a version that is quite recent, and will therefore let you know automatically if you get the interrupt configuration wrong?


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 16, 2016

I don't get any assertion failure. My issue is I get no notifications. Should I revert back to using events? sijomon


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 16, 2016

Codes I use are from the version 9.0 sijomon


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by rtel on March 16, 2016

...and you have configASSERT() defined? I can't see it defined in the config file you posted.

There is nothing obviously wrong in your code that I can see.


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 16, 2016
Let me see.I think I have not done that.I will let you know tomorrow. configASSERT() is a recent advancement, is it not? It's off office hours here now.
By the way is there any port for FreeRTOS+udp for TIVA TM4C1294NCPDT? Especially hookup and init functions to the Ethernet Controller? I could see them for some other microcontrollers in the FreeRTOS plus folder in the package, but not for this series. I am somewhat a novice towards FreeRTOS, though not to operating systems as such. 
I have gone through the TIVA ethernet controller peripheral internals as well as their peripheral support library, but not to the UDP implementation of FreeRTOS. If somebody could probably help me out in gelling the TIVA peripheral LLDs with the FreeRTOS, its also very much appreaciated.

regards, Sijomon


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 17, 2016

How would that help anyway?


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 17, 2016

You are right. I also doubted. Now I will have to go and check the interrupt priority settings in the register locations. Let me see. sijomon


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 17, 2016

This is what is there in the datasheet:

Nested Vectored Interrupt Controller (NVIC) This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC supports: ■ 106 interrupts. ■ A programmable priority level of 0-7 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority......

Now when I checked all the int priorities are by default set to 0, which is the highest priority.

NVICSYSPRI1 0x00000000 System Handler Priority 1 [Memory Mapped] NVICSYSPRI1USAGE 000 Usage Fault Priority NVICSYSPRI1BUS 000 Bus Fault Priority NVICSYSPRI1MEM 000 Memory Management Fault Priority NVICSYSPRI2 0x00000000 System Handler Priority 2 [Memory Mapped] NVICSYSPRI2SVC 000 SVCall Priority NVICSYSPRI3 0xE0E00000 System Handler Priority 3 [Memory Mapped] NVICSYSPRI3TICK 111 SysTick Exception Priority NVICSYSPRI3PENDSV 111 PendSV Priority NVICSYSPRI3_DEBUG 000 Debug Priority

And this is what my debugger says. System handler and Pendsv interrupt priorities are set to be 111.(0x07)

Also NVICINTCTRL 0x1441A81E Interrupt Control and State [Memory Mapped] NVICINTCTRLNMISET 0 NMI Set Pending NVICINTCTRLPENDSV 1 PendSV Set Pending NVICINTCTRLUNPENDSV 0 PendSV Clear Pending NVICINTCTRLPENDSTSET 1 SysTick Set Pending NVICINTCTRLPENDSTCLR 0 SysTick Clear Pending NVICINTCTRLISRPRE 0 Debug Interrupt Handling NVICINTCTRLISRPEND 1 Interrupt Pending NVICINTCTRLVECPEN 00011010 Interrupt Pending Vector Number NVICINTCTRLRETBASE 1 Return to Base NVICINTCTRLVECACT 00011110 Interrupt Pending Vector Number

This is the state.

I have not gone deep into the OS code to dig out what it is doing with system handler as well as pendsv. Could you help. Where this kernel interrupt priority is programmed? and what it does exactly?

Sijomon


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by rtel on March 17, 2016

The kernel interrupt priority (PendSV and SysTick) is set in the FreeRTOS port layer - and must be the lowest possible interrupt priority.

Any interrupt that makes use of the FreeRTOS API cannot be left at its default priority, and must be set to a priority at or below configMAXSYSCALLINTERRUPT_PRIORITY.

As there are priorities 0 to 7 on your device then there must it must implement three priority bits (or the possible 8, although in practice 3 or 4 bits seems to be the norm).


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 17, 2016

Thats all right. I think all the settings are working as per the freertos requires and is found to be correct from the regstatus as shown below.

NVICINTCTRL 0x1441A81E Interrupt Control and State [Memory Mapped] NVICINTCTRLNMISET 0 NMI Set Pending NVICINTCTRLPENDSV 1 PendSV Set Pending NVICINTCTRLUNPENDSV 0 PendSV Clear Pending NVICINTCTRLPENDSTSET 1 SysTick Set Pending NVICINTCTRLPENDSTCLR 0 SysTick Clear Pending NVICINTCTRLISRPRE 0 Debug Interrupt Handling NVICINTCTRLISRPEND 1 Interrupt Pending NVICINTCTRLVECPEN 00011010 Interrupt Pending Vector Number NVICINTCTRLRETBASE 1 Return to Base NVICINTCTRLVECACT 00011110 Interrupt Pending Vector Number

As said in the above post, Here are the NVIC interrupt control states pulled out from the CCS debugger. PendSV set pending is 1 as shown. Still what could be wrong? I hope I don't need to look into the port files for ccs/ARM_CM4F and can blindly believe its 100% correct.

Sijomon


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by rtel on March 17, 2016

Is it possible interrupts are disabled, or that you are in a critical regions, or the scheduler is suspended? Try stepping through the tick interrupt to see what it does.


xTaskNotifyWait never gets notification in TIVA TM4C1294

Posted by sijomon1234 on March 18, 2016

By default all peripheral interrupts' priority is set to be 0,that is to the highest priority. Exception was caught with the configASSERT() technique. Later the priorities were changed to some higher values (demoted to lower priority) than the systick int priority. Now everything works smoothly. Thanks for your timely help and coming up with such a wonderful engineered code and ofcourse a commendable support from your side. wish you a great success in your endevour.

regards, Sijomon


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