Quality RTOS & Embedded Software

 Real time embedded FreeRTOS RSS feed 
Real time embedded FreeRTOS mailing list 
Quick Start Supported MCUs PDF Books Trace Tools Ecosystem TCP & FAT Training


PIC interrupt priorities

Posted by Nobody/Anonymous on November 16, 2004
Just getting started looking at the PIC 18 port to see if it will fit my needs. Thanks for all the work by the way. Very cool.

I ran across something that I am a "bit" confused on. (Pardon the pun...) The UART RX and TX interrupts are set as low priority interrupts (TXIP and RXIP bits = 0). And the ISR function is appropriately named "prvLowInterrupt" but the pragma that surrounds the ISR locates this code at 0x08, which according to my datasheet is the vector for the high priority interrupt. Have I missed something? I am not too new to PICs but my past applications were simple enough to employ polling. So I am new to interrupts in the PIC. Has my datasheet led me astray or might there be an error (perhaps in my head) here.

RE: PIC interrupt priorities

Posted by Richard on November 16, 2004
The PIC18 has a compatibility mode which effectively switches off this interrupt prioritisation mechanism - this is the default. When interrupt priorities are not enabled the chip operates as per the mid range devices, and all interrupt vector to 0x08.

See the description of the bit IPEN (RCON<7>) and the interrupt section of the PIC18 manual for more details.

Thanks for you comments.


RE: PIC interrupt priorities

Posted by Nobody/Anonymous on November 17, 2004
Doh. Didn't catch that on my first read through the interrupt section. Thanks for setting me straight.

I plan to add the PortB OnChange Interrupt. Should I just add it to the low priority interrupts, or would there be any advantage to handling it as a low priority and having the tick interrupt at a high priority? Seems like I would have to implement nested interrupts to use both priority levels.

Thank again.

RE: PIC interrupt priorities

Posted by Richard on November 17, 2004
Keeping it as a low priority would be the easiest - nesting the interrupts would require a larger stack (stating the obvious I know).

Provided the new ISR is kept short it is unlikely to cause a problem. If the interrupts occur at the same time you may have a small jitter in the tick period, but as the tick runs from a free running timer any timing error will not accumulate over time – the next tick will still occur at the correct time.


[ Back to the top ]    [ About FreeRTOS ]    [ Sitemap ]    [ ]

Copyright (C) 2004-2010 Richard Barry. Copyright (C) 2010-2016 Real Time Engineers Ltd.
Any and all data, files, source code, html content and documentation included in the FreeRTOSTM distribution or available on this site are the exclusive property of Real Time Engineers Ltd.. See the files license.txt (included in the distribution) and this copyright notice for more information. FreeRTOSTM and FreeRTOS.orgTM are trade marks of Real Time Engineers Ltd.

Latest News:

FreeRTOS V9.0.0 is now available for download.

Free TCP/IP and file system demos for the RTOS

Sponsored Links

⇓ Now With No Code Size Limit! ⇓
⇑ Free Download Without Registering ⇑

FreeRTOS Partners

ARM Connected RTOS partner for all ARM microcontroller cores

Renesas Electronics Gold Alliance RTOS Partner.jpg

Microchip Premier RTOS Partner

RTOS partner of NXP for all NXP ARM microcontrollers

Atmel RTOS partner supporting ARM Cortex-M3 and AVR32 microcontrollers

STMicro RTOS partner supporting ARM7, ARM Cortex-M3, ARM Cortex-M4 and ARM Cortex-M0

Xilinx Microblaze and Zynq partner

Silicon Labs low power RTOS partner

Altera RTOS partner for Nios II and Cortex-A9 SoC

Freescale Alliance RTOS Member supporting ARM and ColdFire microcontrollers

Infineon ARM Cortex-M microcontrollers

Texas Instruments MCU Developer Network RTOS partner for ARM and MSP430 microcontrollers

Cypress RTOS partner supporting ARM Cortex-M3

Fujitsu RTOS partner supporting ARM Cortex-M3 and FM3

Microsemi (previously Actel) RTOS partner supporting ARM Cortex-M3

Atollic Partner

IAR Partner

Keil ARM Partner

Embedded Artists