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Interrupt nesting for SAM7s port

Posted by https://www.google.com/accounts on November 8, 2011
Hello,

I have a need to enable interrupt nesting in the SAM 7S port of Free RTOS.

From the code sample here:

http://gandalf.arubi.uni-kl.de/avr_projects/arm_projects/index_at91.html#at91uart_and_aic

it describes a technique in the ISR to store the registers to the IRQ stack, then enable interrupt nesting. At the end of the Interrupt routine, the registers are restored and interrupt nesting is disabled.

I am trying to figure out the proper way to integrate these macros into portISR.c (vPreemptiveTick function) and how to get them to work with the existing portSAVE_CONTEXT() / portRESTORE_CONTEXT() macros.

so far I've included the interrupt nesting macros outside portSAVE_CONTEXT() / portRESTORE_CONTEXT() - and inside- both crash the kernel. I'm starting to dig further now.

Any guidance would be great. After this is working I would be more than happy to contribute back interrupt nesting capability for the SAM7s port.

Thank you,
Brent Picasso

-----------------------


Macros from example that enable/disable interrupt nesting plus /save/restore




/******************************************************************************
*
* MACRO Name: ISR_STORE()
*
* Description:
* This MACRO is used upon entry to an ISR with interrupt nesting.
* Should be used together with ISR_ENABLE_NEST(). The MACRO
* performs the following steps:
*
* 1 - Save the non-banked registers r0-r12 and lr onto the IRQ stack.
*
*****************************************************************************/
#define ISR_STORE() asm volatile( \
"STMDB SP!,{R0-R12,LR}\n" )

/******************************************************************************
*
* MACRO Name: ISR_RESTORE()
*
* Description:
* This MACRO is used upon exit from an ISR with interrupt nesting.
* Should be used together with ISR_DISABLE_NEST(). The MACRO
* performs the following steps:
*
* 1 - Load the non-banked registers r0-r12 and lr from the IRQ stack.
* 2 - Adjusts resume adress
*
*****************************************************************************/
#define ISR_RESTORE() asm volatile( \
"LDMIA SP!,{R0-R12,LR}\n" \
"SUBS R15,R14,#0x0004\n" )

/******************************************************************************
*
* MACRO Name: ISR_ENABLE_NEST()
*
* Description:
* This MACRO is used upon entry from an ISR with interrupt nesting.
* Should be used after ISR_STORE.
*
*****************************************************************************/
#define ISR_ENABLE_NEST() asm volatile( \
"MRS LR, SPSR \n" \
"STMFD SP!, {LR} \n" \
"MSR CPSR_c, #0x1F \n" \
"STMFD SP!, {LR} " )

/******************************************************************************
*
* MACRO Name: ISR_DISABLE_NEST()
*
* Description:
* This MACRO is used upon entry from an ISR with interrupt nesting.
* Should be used before ISR_RESTORE.
*
*****************************************************************************/
#define ISR_DISABLE_NEST() asm volatile( \
"LDMFD SP!, {LR} \n" \
"MSR CPSR_c, #0x92 \n" \
"LDMFD SP!, {LR} \n" \
"MSR SPSR_cxsf, LR \n" )


RE: Interrupt nesting for SAM7s port

Posted by https://www.google.com/accounts on November 11, 2011
Can anyone provide guidance on this? FreeRTOS developers?

Thank you.

RE: Interrupt nesting for SAM7s port

Posted by https://www.google.com/accounts on November 14, 2011
Bump - this is critical for proper performance of the system I'm developing. Any help is appreciated!

RE: Interrupt nesting for SAM7s port

Posted by Richard on November 15, 2011
I'm afraid this is not something I have done myself so can't provide a quick solution. I know several manufacturers have application notes on nesting interrupts on ARMv4 cores (such as that found in the ARM7), but it looks like you have one yourself. While on the ARMv7M (such as that found in ARM Cortex-M devices) nesting with and without an RTOS is simple and supported, on the ARM7 it is complex enough without an RTOS and I believe that even ARMs own RTOS does not support interrupt nesting.

My only advice would be to try and keep your interrupt service routines as absolutely short as possible, and don't do any processing in them other than to wake a task that can then do the processing at task, rather than interrupt level, so interrupts remain enabled most of the time. If you make the tasks that do the processing high enough priority you can do the processing contiguous in time, just as if it were done in the interrupt, by making the interrupt return directly into the handling task.

Regards.

RE: Interrupt nesting for SAM7s port

Posted by https://www.google.com/accounts on November 16, 2011
Richard,

Thanks for your reply. It's given me some ideas on thinning out one of my interrupt handlers back into a task and seeing what results I get there.

My original concern was to enable interrupt nesting so the FreeRTOS vPreemtiveTick could be interrupted, in order to minimize latencies in my timing sensitive app.

I need to profile vPreemtiveTick so I can characterize what the maximum latency would be under worse case condition (if my timing sensitive interrupt fires *just after* vPreemtiveTick starts).

But, there's the USB CDC interrupt handler to deal with as well..

I'll report back with my findings.

Thanks again!
Brent

RE: Interrupt nesting for SAM7s port

Posted by Piero B on November 21, 2011
Hi

there is also this discussion:
https://sourceforge.net/projects/freertos/forums/forum/382005/topic/4831083/index/page/1

i'd like to discuss about this argument

thanks
Bye
Piero


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