Quality RTOS & Embedded Software

 Real time embedded FreeRTOS RSS feed 
Real time embedded FreeRTOS mailing list 
Quick Start Supported MCUs PDF Books Trace Tools Ecosystem TCP & FAT Training




Loading

Linker STM32 MPU bin 402MB

Posted by vinimac on October 26, 2016

Hi guys, I'm using this linker script and result xxx.bin file give 402MB. I took from CORTEXMPUSimulatorKeilGCC example.

~~~ /* Specify the memory areas */ MEMORY { ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K }

/* Variables used by FreeRTOS-MPU. */ PrivilegedFunctionsRegionSize = 32K; PrivilegedDataRegionSize = 512;

FLASHsegmentstart = ORIGIN( ROM ); FLASHsegmentend = FLASHsegmentstart + LENGTH( ROM );

privilegedfunctionsstart = ORIGIN( ROM ); privilegedfunctionsend = privilegedfunctionsstart + PrivilegedFunctionsRegionSize;

SRAMsegmentstart = ORIGIN( RAM ); SRAMsegmentend = SRAMsegmentstart + LENGTH( RAM );

privilegeddatastart = ORIGIN( RAM ); privilegeddataend = ORIGIN( RAM ) + PrivilegedDataRegionSize;

/* * The '__stack' definition is required by crt0, do not remove it. */ __stack = ORIGIN(RAM) + LENGTH(RAM); _estack = __stack;

/* * Default stack sizes. * These are used by the startup in order to allocate stacks * for the different modes. */

_MainStack_Size = 2048 ;

PROVIDE ( MainStackSize = __MainStack_Size ) ;

_MainStackLimit = __stack - __MainStack_Size ;

/*"PROVIDE" allows to easily override these values from an object file or the command line. */ PROVIDE ( MainStackLimit = __MainStack_Limit ) ;

/* * There will be a link error if there is not this amount of * RAM free at the end. */ MinimumStack_Size = 1024 ;

/* * Default heap definitions. * The heap start immediately after the last statically allocated * .sbss/.noinit section, and extends up to the main stack limit. */ PROVIDE ( HeapBegin = endnoinit ) ; PROVIDE ( HeapLimit = _stack - __MainStack_Size ) ;

/* * The entry point is informative, for debuggers and simulators, * since the Cortex-M vector points to it anyway. */ ENTRY(Reset_Handler)

/* Sections Definitions */

SECTIONS { /* * For Cortex-M devices, the beginning of the startup code is stored in * the .isrvector section, which goes to ROM */ privilegedfunctions : { . = ALIGN(4); isrvector = .; KEEP(*(.isrvector)) *(privilegedfunctions) . = ALIGN(4);

    /* Non privileged code is after _Privileged_Functions_Region_Size. */
    __privileged_functions_actual_end__ = .;
    . = _Privileged_Functions_Region_Size;
} > ROM



.text :
{
    . = ALIGN(4);


    /*
     * This section is here for convenience, to store the
     * startup code at the beginning of the flash area, hoping that
     * this will increase the readability of the listing.
     */
    KEEP(*(.after_vectors .after_vectors.*))    /* Startup code and ISR */

    . = ALIGN(4);

    /*
     * These are the old initialisation sections, intended to contain
     * naked code, with the prologue/epilogue added by crti.o/crtn.o
     * when linking with startup files. The standalone startup code
     * currently does not run these, better use the init arrays below.
     */
    KEEP(*(.init))
    KEEP(*(.fini))

    . = ALIGN(4);

    /*
     * The preinit code, i.e. an array of pointers to initialisation
     * functions to be performed before constructors.
     */
    PROVIDE_HIDDEN (__preinit_array_start = .);

    /*
     * Used to run the SystemInit() before anything else.
     */
    KEEP(*(.preinit_array_sysinit .preinit_array_sysinit.*))

    /*
     * Used for other platform inits.
     */
    KEEP(*(.preinit_array_platform .preinit_array_platform.*))

    /*
     * The application inits. If you need to enforce some order in
     * execution, create new sections, as before.
     */
    KEEP(*(.preinit_array .preinit_array.*))

    PROVIDE_HIDDEN (__preinit_array_end = .);

    . = ALIGN(4);

    /*
     * The init code, i.e. an array of pointers to static constructors.
     */
    PROVIDE_HIDDEN (__init_array_start = .);
    KEEP(*(SORT(.init_array.*)))
    KEEP(*(.init_array))
    PROVIDE_HIDDEN (__init_array_end = .);

    . = ALIGN(4);

    /*
     * The fini code, i.e. an array of pointers to static destructors.
     */
    PROVIDE_HIDDEN (__fini_array_start = .);
    KEEP(*(SORT(.fini_array.*)))
    KEEP(*(.fini_array))
    PROVIDE_HIDDEN (__fini_array_end = .);
    . = ALIGN(4);

    . = ALIGN(4);

    *(.text*)            /* all remaining code */

    *(vtable)                   /* C++ virtual tables */

} >ROM

.rodata :
{
    *(.rodata*)        /* read-only data (constants) */
} >ROM

.glue :
{
    KEEP(*(.eh_frame*))

    /*
    * Stub sections generated by the linker, to glue together
    * ARM and Thumb code. .glue_7 is used for ARM code calling
    * Thumb code, and .glue_7t is used for Thumb code calling
    * ARM code. Apparently always generated by the linker, for some
    * architectures, so better leave them here.
    */
    *(.glue_7)
    *(.glue_7t)
} >ROM

/* ARM magic sections */
.ARM.extab :
{
   *(.ARM.extab* .gnu.linkonce.armextab.*)
} > ROM

__exidx_start = .;
.ARM.exidx :
{
   *(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ROM
__exidx_end = .;

. = ALIGN(4);
_etext = .;
__etext = .;

/*
 * This address is used by the startup code to
 * initialise the .data section.
 */
_sidata = _etext;

/* MEMORY_ARRAY */
/*
.ROarraySection :
{
    *(.ROarraySection .ROarraySection.*)
} >MEMORY_ARRAY
*/


privileged_data :
{
    *(privileged_data)
    /* Non kernel data is kept out of the first _Privileged_Data_Region_Size
    bytes of SRAM. */
    __privileged_data_actual_end__ = .;
    . = _Privileged_Data_Region_Size;
} > RAM

/*
 * The initialised data section.
 * The program executes knowing that the data is in the RAM
 * but the loader puts the initial values in the ROM (inidata).
 * It is one task of the startup to copy the initial values from
 * ROM to RAM.
 */
.data  : AT ( _sidata )
{
    . = ALIGN(4);

    /* This is used by the startup code to initialise the .data section */
    _sdata = . ;            /* STM specific definition */
    __data_start__ = . ;
    *(.data_begin .data_begin.*)

    *(.data .data.*)

    *(.data_end .data_end.*)
    . = ALIGN(4);

    /* This is used by the startup code to initialise the .data section */
    _edata = . ;            /* STM specific definition */
    __data_end__ = . ;

} >RAM


/*
 * The uninitialised data section. NOLOAD is used to avoid
 * the "section `.bss' type changed to PROGBITS" warning
 */
.bss (NOLOAD) :
{
    . = ALIGN(4);
    __bss_start__ = .;      /* standard newlib definition */
    _sbss = .;              /* STM specific definition */
    *(.bss_begin .bss_begin.*)

    *(.bss .bss.*)
    *(COMMON)

    *(.bss_end .bss_end.*)
    . = ALIGN(4);
    __bss_end__ = .;        /* standard newlib definition */
    _ebss = . ;             /* STM specific definition */
} >RAM

.noinit (NOLOAD) :
{
    . = ALIGN(4);
    _noinit = .;

    *(.noinit .noinit.*)

     . = ALIGN(4) ;
    _end_noinit = .;
} > RAM

/* Mandatory to be word aligned, _sbrk assumes this */
PROVIDE ( end = _end_noinit ); /* was _ebss */
PROVIDE ( _end = _end_noinit );
PROVIDE ( __end = _end_noinit );
PROVIDE ( __end__ = _end_noinit );
PROVIDE ( ROM_DATA_START = __data_start__ );

/*
 * Used for validation only, do not allocate anything here!
 *
 * This is just to check that there is enough RAM left for the Main
 * stack. It should generate an error if it's full.
 */
._check_stack :
{
    . = ALIGN(4);

    . = . + _Minimum_Stack_Size ;

    . = ALIGN(4);
} >RAM

/* After that there are only debugging sections. */

/* This can remove the debugging information from the standard libraries */
/*
DISCARD :
{
 libc.a ( * )
 libm.a ( * )
 libgcc.a ( * )
 }
 */

/* Stabs debugging sections.  */
.stab          0 : { *(.stab) }
.stabstr       0 : { *(.stabstr) }
.stab.excl     0 : { *(.stab.excl) }
.stab.exclstr  0 : { *(.stab.exclstr) }
.stab.index    0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment       0 : { *(.comment) }
/*
 * DWARF debug sections.
 * Symbols in the DWARF debugging sections are relative to the beginning
 * of the section so we begin them at 0.
 */
/* DWARF 1 */
.debug          0 : { *(.debug) }
.line           0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo  0 : { *(.debug_srcinfo) }
.debug_sfnames  0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges  0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev   0 : { *(.debug_abbrev) }
.debug_line     0 : { *(.debug_line) }
.debug_frame    0 : { *(.debug_frame) }
.debug_str      0 : { *(.debug_str) }
.debug_loc      0 : { *(.debug_loc) }
.debug_macinfo  0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames  0 : { *(.debug_varnames) }

} ~~~

Does anyone have a working Linker Script for the STM32 family and the MPU-port? Or an explanation for the behavior?


Linker STM32 MPU bin 402MB

Posted by edwards3 on October 26, 2016

probably the bin file is just filling the memory between valid addresses with 0s. Use the elf file to program the chip.


[ Back to the top ]    [ About FreeRTOS ]    [ Sitemap ]    [ ]




Copyright (C) 2004-2010 Richard Barry. Copyright (C) 2010-2016 Real Time Engineers Ltd.
Any and all data, files, source code, html content and documentation included in the FreeRTOSTM distribution or available on this site are the exclusive property of Real Time Engineers Ltd.. See the files license.txt (included in the distribution) and this copyright notice for more information. FreeRTOSTM and FreeRTOS.orgTM are trade marks of Real Time Engineers Ltd.

Latest News:

FreeRTOS V9.0.0 is now available for download.


Free TCP/IP and file system demos for the RTOS


Sponsored Links

⇓ Now With No Code Size Limit! ⇓
⇑ Free Download Without Registering ⇑


FreeRTOS Partners

ARM Connected RTOS partner for all ARM microcontroller cores

Renesas Electronics Gold Alliance RTOS Partner.jpg

Microchip Premier RTOS Partner

RTOS partner of NXP for all NXP ARM microcontrollers

Atmel RTOS partner supporting ARM Cortex-M3 and AVR32 microcontrollers

STMicro RTOS partner supporting ARM7, ARM Cortex-M3, ARM Cortex-M4 and ARM Cortex-M0

Xilinx Microblaze and Zynq partner

Silicon Labs low power RTOS partner

Altera RTOS partner for Nios II and Cortex-A9 SoC

Freescale Alliance RTOS Member supporting ARM and ColdFire microcontrollers

Infineon ARM Cortex-M microcontrollers

Texas Instruments MCU Developer Network RTOS partner for ARM and MSP430 microcontrollers

Cypress RTOS partner supporting ARM Cortex-M3

Fujitsu RTOS partner supporting ARM Cortex-M3 and FM3

Microsemi (previously Actel) RTOS partner supporting ARM Cortex-M3

Atollic Partner

IAR Partner

Keil ARM Partner

Embedded Artists