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SAMA5D2 Full Demo DDRAM

Posted by moreon1 on October 28, 2016

I am able to successfully build, download, and run the SAMA5D2 Full demo from SRAM on my SAMA5D2 Xplained evaluation board. However, if I switch to run from DDRAM instead, I am able to build and download the Full demo, but it fails runtime checks.The first is the BlockTime test. If I change the bktALLOWABLE_MARGIN from 15 to 1000, the task checks will pass. Unfortunately, then the Dynamic task will fail. Based upon this information, I am assuming that there is an execution timing problem when running from DDRAM. It appears that the ICACHE and DCACHE are not enabled. Could this be the problem? Any samples to get the Full demo running from DDRAM on the evaluation board?


SAMA5D2 Full Demo DDRAM

Posted by rtel on October 28, 2016

Have you tried enabling the caches? They will not have been enabled because they were not needed while running from internal RAM.


SAMA5D2 Full Demo DDRAM

Posted by moreon1 on October 31, 2016

I tried to enable the caches by calling cp15enableicache(), but it generates an exception handled by the AbortHandler.


SAMA5D2 Full Demo DDRAM

Posted by rtel on October 31, 2016

When the function is called, or when you execute the application after the cache is enabled?


SAMA5D2 Full Demo DDRAM

Posted by moreon1 on October 31, 2016

As soon as I attempt to return from the cp15enableicache() function.


SAMA5D2 Full Demo DDRAM

Posted by moreon1 on October 31, 2016

Correction. It appears that the function returns, but fails a little bit later. I'm tacking down the specific code now...


SAMA5D2 Full Demo DDRAM

Posted by moreon1 on October 31, 2016

Tracing down exact location that causes exception will take time. Once ICache is enabled, I cannot even single step at the C code level, nor do breakpoints work. I am having to single step at the ASM level, into every function, never over.


SAMA5D2 Full Demo DDRAM

Posted by moreon1 on October 31, 2016

Digging deeper, I found a boardcfgmmu() function as part of Atmel's software support package library. It configures the MMU, then enables ICache, MMU, and finally DCache. I take it this is uncharted territory for the FreeRTOS demo on the SAMA5D2 Xplained evaluation board? Is it a bit strange, though, as the port includes IAR linker files and Debugger macro files for both SRAM and DDRAM configurations. And pointers would be welcomed.


SAMA5D2 Full Demo DDRAM

Posted by rtel on October 31, 2016

Other Cortex-A demos use the caches without any problem. As said before the caches were not turned on in that demo because they were not needed when running from internal RAM.


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