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FreeRTOS with dsPIC has periodic resets

Posted by c_welch on September 27, 2014

I'm having problems with FreeRTOS periodically reseting for no apparent reason. Even running the demo project contained in the FreeRTOS distribution shows the same problem. It will run for an hour or two and then the debugger halts showing "No user code at 0x0"

I'm using MPLAB X IDE v2.15, xc16-gcc v1.21 and ICD 3 with a dsPIC33FJ256GP710A on the Microchip Explorer 16 board. FreeRTOS version is 8.1.2.

I picked up the documentation package and ported the very simple two task example from the "Using the FreeRTOS Real Time Kernel - A Practical Guide" PIC32 edition and it shows the same reset problem after running for a while.

I've identified that it isn't my hardware or MPLAB environment as the Microchip Explorer 16 demo ran for close to a day without a reset.

I added the interrupt trap file from the Explorer 16 demo which has system interrupt traps with infinite while loops for the things that cause a processor reset (E.g. address, stack, math errors) but none of the interrupts are entered when the FreeRTOS application halts.

I've ensured the project has the MPLABDSPICPORT definition defined in the pre processing and messages "Define C macrons" option as I saw a post that indicated the author's resets were due to the lack of this definition.

The problem can be replicated by simply running the FreeRTOS dsPIC demo application for a while with the debugger on. You'll find eventually the session halts.

Here is the configuration and source for the simple ported FreeRTOS that is the simplest I've been able to setup to replicate the problem based on the initial task logic from the FreeRTOS documentation.

Start this up with the debugger and after a few hours you'll find the session halted and a message indicating no source code at PC 0x0:

~~~~~~~~~~~~~~~~~~~

define configUSE_PREEMPTION 1
define configUSEIDLEHOOK 1
define configUSETICKHOOK 0
define configTICKRATEHZ ( ( TickType_t ) 1000 )
define configCPUCLOCKHZ ( ( unsigned long ) 25000000 ) /* Fosc / 2 */
define configMAX_PRIORITIES ( 4 )
define configMINIMALSTACKSIZE ( 240 )
define configTOTALHEAPSIZE ( ( size_t ) 10240 )
define configMAXTASKNAME_LEN ( 5 )
define configUSETRACEFACILITY 0
define configUSE16BIT_TICKS 1
define configIDLESHOULDYIELD 1
define configCHECKFORSTACK_OVERFLOW 1

/* Co-routine definitions. */

define configUSECOROUTINES 0

/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */

define INCLUDE_vTaskPrioritySet 1
define INCLUDE_uxTaskPriorityGet 0
define INCLUDE_vTaskDelete 0
define INCLUDE_vTaskCleanUpResources 0
define INCLUDE_vTaskSuspend 1
define INCLUDE_vTaskDelayUntil 1
define INCLUDE_vTaskDelay 1
define configKERNELINTERRUPTPRIORITY 0x01

~~~~~~~~~~~~~~~~~~~~~~~~

and the main.c:

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /* * File: main.c * Author: cwelch * * Created on September 24, 2014, 9:55 PM */

include
include
include "FreeRTOS.h"
include "task.h"
define mainDELAYLOOPCOUNT (0xfffff)

/-----------------------------------------------------------/ void vApplicationIdleHook( void ) { ; } /-----------------------------------------------------------/

void vTask1(void *pvParameter) { // const char *pcTaskName = "Task 2 is runningn"; volatile unsigned long ul; while(1) { for (ul = 0; ul < mainDELAYLOOPCOUNT; ul++) { ; } } }

void vTask2(void *pvParameter) { // const char *pcTaskName = "Task 2 is runningn"; volatile unsigned long ul;

while(1)
{
    for (ul = 0; ul < mainDELAY_LOOP_COUNT; ul++)
    {
        ;
    }
}

} /* * */ int main(int argc, char** argv) {

//vTask1();
xTaskCreate(vTask1, "TSK1", 240, NULL, 1, NULL);
xTaskCreate(vTask2, "TSK2", 240, NULL, 1, NULL);

// Should run for ever after this
vTaskStartScheduler();

// Will only reach here if there is insufficient heap available to start the scheduler.
return (EXIT_FAILURE);

} ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

I have most of my application now working under FreeRTOS, but need to address this last problem of stability. It is an engine controller and I can't have it spontaneously resetting.

Thanks in advance for your assistance!

Chris

~~~~~~~~~~~~~~~~~~~~~~~~~~~


FreeRTOS with dsPIC has periodic resets

Posted by rtel on September 27, 2014

We can try running the standard demo here. What is the part number of the dsPIC you are using, and which hardware platform are you running it on?

Regards.


FreeRTOS with dsPIC has periodic resets

Posted by c_welch on September 27, 2014

Part number is dsPIC33FJ256GP710A, the default part that comes with the Explorer 16

Running it on the Explorer 16.


FreeRTOS with dsPIC has periodic resets

Posted by c_welch on September 28, 2014

Some additional information to reproduce. I negelected to mention that I have the free compiler version, so I had to turn off the level 2 optimization to supress the build warnings.

Here are the steps I used:

1 Extract FreeRTOSV8.1.2 2 Start MPLAB X IDE, import MPLAB v8 Project dsPIC_MPLAB *.mcp file from the demos 3 Leave device selection as is 4 Select ICD 3 device 5 Select XC16 v1.21 6 Leave all names and folder defaulted, Finish 7 Set configuration customize, change compiler optimization level to 0 8 Loop back pins 2&3 on RS232 connector 9 Press "Debug project button"

Project will load and give warning of target difference (dspic33FJ256GP710a on explorer 16 vs project dspic33FJ256GP710), press OK and load anyway

Leave running, LCD shows 80 ns max jitter

Eventually, debugger will halt showing no source code at PC 0x0

Target halted fairly quickly this time (within 10 minutes).

I've put the load directly onto the device so it will run without the debugger attached and get similar resets.


FreeRTOS with dsPIC has periodic resets

Posted by c_welch on September 30, 2014

The problem here relates to importing projects into MPLAB X. It has been a while since I've used MPLAB, but I recall the older version of MPLAB used to allow you to setup the chip configuration as part of the project setup.

That is no longer the case and the chip configuration settings are not brought in with the project when you do the import.

That leaves the watch dog active (on by default) causing the resets.

You now have to use the configuration generator and put the setup into a header file or manually code the settings.

Heads up if you are using the new tools with these materials.


FreeRTOS with dsPIC has periodic resets

Posted by rtel on September 30, 2014

Thanks for the information. I thought the settings were actually in the source file rather than the project, but having just looked I see not. They are for other PIC projects, but the dsPIC project is still provided in MPLAB 8 format.

It would be helpful if you could post the settings you have added.

Regards.


FreeRTOS with dsPIC has periodic resets

Posted by c_welch on October 10, 2014

Here is the config file I'm using:

~~~~~~~~~~~~~~~~~~~~ // DSPIC33EP512MU810 Configuration Bit Settings

// 'C' source line config statements

include

// FGS

pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
pragma config GSS = OFF // General Segment Code-Protect bit (General Segment Code protect is disabled)
pragma config GSSK = OFF // General Segment Key bits (General Segment Write Protection and Code Protection is Disabled)

// FOSCSEL

pragma config FNOSC = FRCDIVN // Initial Oscillator Source Selection Bits (Internal Fast RC (FRC) Oscillator with postscaler)
pragma config IESO = ON // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)

// FOSC

pragma config POSCMD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
pragma config IOL1WAY = ON // Peripheral pin select configuration (Allow only one reconfiguration)
pragma config FCKSM = CSECMD // Clock Switching Mode bits (Clock switching is enabled,Fail-safe Clock Monitor is disabled)

// FWDT

pragma config WDTPOST = PS32768 // Watchdog Timer Postscaler Bits (1:32,768)
pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
pragma config PLLKEN = ON // PLL Lock Wait Enable bit (Clock switch to PLL source will wait until the PLL lock signal is valid.)
pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
pragma config FWDTEN = OFF // Watchdog Timer Enable bit (Watchdog timer always enabled)

// FPOR

pragma config FPWRT = PWR128 // Power-on Reset Timer Value Select bits (128ms)
pragma config BOREN = ON // Brown-out Reset (BOR) Detection Enable bit (BOR is enabled)
pragma config ALTI2C1 = OFF // Alternate I2C pins for I2C1 (SDA1/SCK1 pins are selected as the I/O pins for I2C1)
pragma config ALTI2C2 = OFF // Alternate I2C pins for I2C2 (SDA2/SCK2 pins are selected as the I/O pins for I2C2)

// FICD

pragma config ICS = PGD2 // ICD Communication Channel Select bits (Communicate on PGEC2 and PGED2)
pragma config RSTPRI = PF // Reset Target Vector Select bit (Device will obtain reset instruction from Primary flash)
pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)

// FAS

pragma config AWRP = OFF // Auxiliary Segment Write-protect bit (Auxiliary program memory is not write-protected)
pragma config APL = OFF // Auxiliary Segment Code-protect bit (Aux Flash Code protect is disabled)
pragma config APLK = OFF // Auxiliary Segment Key bits (Aux Flash Write Protection and Code Protection is Disabled)

~~~~~~~~~~~~~~~~~~~~~~~~


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