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Context

It is difficult to arrive at a conclusive performance comparison between two embedded processors of differing architecture. To start with you have to define what is meant by performance. For example, this could be the frequency at which a particular task such as the control of a motor can be performed. Such a task would typically include interrupt latency, peripheral performance, memory access speed, table lookup and mathematical calculation efficiency, etc.

Such a course definition compares far more than the CPU core. Alternatively a more abstract measure of say measuring "millions of instructions per second" (MIPS) is particularly unhelpful when comparing RISC with CISC architectures, architectures with and without a cache, or when comparing systems programmed in a high level language. Quoted Dhrystone figures are not always easy to come by and may be suspect unless independently verified.

The tests documented here attempt to provide practical information that can be used as part of a comparison process. The tests are performed using the development tools typically used for real embedded application programming - effectively providing information on the "embedded development platform" which includes a particular hardware platform and a particular C compiler. A highly efficient processor is after all wasted if the chosen compiler is weak.

The test results show a 'comparison' of several 'systems' being used in a 'normal' manner.

Most applications can be broken down into a number of smaller components, a lot of which will be common to other applications (for example block memory moves, or mathematical calculations). Most of the tests presented here perform a single small component, allowing individuals to compare the performance of the components relevant to their particular embedded application.

Exactly the same source code was executed on each microcontroller - but the processor clock frequency, memory configuration and C compiler must be taken into account when comparing results. All the presented timing results were obtained using the same digital oscilloscope. Peripheral performance (for example an analogue to digital conversion time) and interrupt latency was not measured as these are usually well documented.




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