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STM32 CortexM3 demo.

Posted by GregK on April 16, 2010

Seem to in demo config for STM32 CortexM3 arch is small bug (rather non consistency) but without side effects.

In FreeRTOSConfig.h

#define configMAX_SYSCALL_INTERRUPT_PRIORITY 191 /* equivalent to 0xb0, or priority 11. */

According http://www.st.com/stonline/products/literature/pm/15491.pdf page 20,
in BASEPRI only bits 7:4 are valid. So I expect rather:

#define configMAX_SYSCALL_INTERRUPT_PRIORITY (11U<<4U) /* equivalent to 0xb0, or priority 11. */
11U<<4U is 0xB0, what is also priority 11.

It is equivalent of 191 (0xBF), since from documentation bits 3:0 are reserved.


RE: STM32 CortexM3 demo.

Posted by Richard on April 16, 2010
The Cortex M3 is designed with 'forward compatibility' in mind (sounds like their marketing dept. got involved in that). This is why the interrupt mechanism is so confusing. The Cortex M3 itself has 8 bits of priority, but different implementations use a different number of bits. In the interest of 'forward compatibility' it is the most significant bits that are actually used, the idea being that code will be portable to future revisions of the cpu that might implement more bits.

The way the code is written is deliberate, and fine as it is. A lot of this code was written before the CMSIS stuff existed, and before most of the documentation on the CM3 was publicly available.


RE: STM32 CortexM3 demo.

Posted by GregK on April 16, 2010
Catch point, thanks.

I expected something better documented like:
((11U<<4U) | 0x0FU)

RE: STM32 CortexM3 demo.

Posted by Richard on April 16, 2010
“I expected something better documented like:
((11U<<4U) | 0x0FU)”

I presume you mean that to be 0xF0, not 0x0F?

That would also depend on where the definition was used. In some cases (like in inline asm code) it cannot be written that way.


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