Dear Richard, Since one of the really hot features (my opinion) of the PIC32MZ is the fact that each interrupt priority CAN (if you configure it so) have its own set of Interrupt Shadow Registers, I was seriously wondering if this could be taken advantage of for FreeRTOS Interrupts (wrapper interrupts normally surrounded by portSAVECONTEXT and portRESTORECONTEXT), if interrupt nesting was turned off. From what I can tell, such support would enable the PIC32MZ to handle short FreeRTOS ISRs in a tiny fraction of the normal time. I realize such a thing is complex and would require the end programmer to follow a different set of policies regarding how FreeRTOS interrupts are coded. Are there any plans to pursue such a thing? Kind regards, Vic Wheeler
This has been discussed, but I’m afraid its not got any further than a discussion, so while I can say its on the the ‘todo’ list, I can’t say when (or if) it will get done (there are a lot of things on the todo list ;o) I don’t think providing shadow register support for individual peripheral interrupts would be difficult if the interrupts didn’t perform a context switch – if a context switch was to be performed then the performance gain would be limited by the need to save/restore the context. What would be more interesting is giving FreeRTOS its own set of shadow registers, in other words, to have interrupts used by FreeRTOS configured to use a shadow set. That could avoid the need for saving/restoring of temporary values, and generally make the scheduling faster. It would need some study though, and result in quite a lot of rework. Regards.
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