Hi, Since I couldn’t find FreeRTOS port for the Cortex-A8 in the net, I’m attemping to make one for the AM335x SoCs. I’m using the demo example for Cortex-A9 as the base and this page http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-proprietary-interrupt-controller.html for little guidiance. In the page, it says configINTERRUPTVECTORADDRESS must be set to the address of a variable that points to a central interrupt handler. What’s a “central interrupt handler”? For configEOI_ADDRESS parameter, I looked in the technical refernce manual of AM335x but no such register exists, so I’m going to set it to the address of a dummy variable. I have configured DMTimer1_1ms as the tick timer. Is there anything else in the A9 port that must be changed to make it work for the A8? Thanks

Since I couldn’t find FreeRTOS port for the Cortex-A8 in the net, I’m attemping to make one for the AM335x SoCs.

I just did a search for “FreeRTOS Beaglebone Black” and there were lots of hits, including near the top https://github.com/steve-kim/BeagleBone

What’s a “central interrupt handler”?

Some interrupt controllers have a separate vector for each interrupt. When this is the case, assuming the interrupt vectors have been populated correctly, the interrupt controller will automatically call the correct interrupt service routine for any interrupt it accepts. That means there are multiple interrupt entry points – one for each vector. Other interrupt controllers do not have the capability to directly vector to the correct handler for any particular interrupt as they only support a single interrupt entry point – what is referred to in the text you reference as the “central interrupt handler”. When this is the case the software implementation of the central interrupt handler has to inspect the interrupt controller registers to determine which interrupt was accepted, and then branch the the appropriate interrupt handler accordingly.

Hi, Thanks for the reply. I have came across that Github repository before, however I could not find port files for the A8 inside…Did I miss something? The AM335x has a vector table for interrupts. I’m inializing the table as follows: ~~~ static unsigned int const vecTbl[14]= { 0xE59FF018, /* Opcode for loading PC with the contents of [PC + 0x18] / 0xE59FF018, / Opcode for loading PC with the contents of [PC + 0x18] / 0xE59FF018, / Opcode for loading PC with the contents of [PC + 0x18] / 0xE59FF018, / Opcode for loading PC with the contents of [PC + 0x18] / 0xE59FF014, / Opcode for loading PC with the contents of [PC + 0x14] / 0xE24FF008, / Opcode for loading PC with (PC – 8) (eq. to while(1)) / 0xE59FF010, / Opcode for loading PC with the contents of [PC + 0x10] / 0xE59FF010, / Opcode for loading PC with the contents of [PC + 0x10] */ (unsigned int)Entry, (unsigned int)UndefInstHandler, (unsigned int)SVC_Handler, (unsigned int)AbortHandler, (unsigned int)IRQHandler, (unsigned int)FIQHandler }; ~~~ I’m guessing there is no need to specify a central interrupt handler in this case.

This looks like a typical Cortex-A vector table, where there is only one IRQ handler (called IRQHandler in your case) which IS the central interrupt handler. If you are not familiar with the Cortex-A architecture then I would recommend referring to the vector table sections of the ARM manuals.