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Semaphores again

Posted by Nobody/Anonymous on December 19, 2005
A while back I posted thread on semaphores and a problem I had whith xSemaphoreTake returning before the waiting time had expired. Barry posted a reply to that but since then I hadn't had much time to have a look at it, but a week ago I got some time again started to reinvestigare the problem. Here are my findings, please comment on any wrong assumptions/conclusions I've come up with.

The setup:
2 tasks, one running at prio 4, the other at 2. he high prio task is used for MP3-playback and basically only releases the CPU for 1 mS every 10-12 mS.

The two tasks share a common resource, an SPI bus which is used to communicate with a memory card and a display.

What happens??
Well, the SPI driver is called from two different tasks.. At the entry of the read and write functions the driver tries to aquire a semaphore. As it turns out the low prio task sometimes misses to aquire the semaphore, even though only 2-5 mS of it's allowed waiting time has passed.

The reason I firgure is this... (In the following T# notation is used, # indicates the priority of the task).

1. T4 aquire the semaphore. Starts to read some data. During the read the processor is released, so that lower prio tasks can be run.
2. T2 runs, and tries to aquire the semaphore.. I has to wait.
3. T4, read is complete and the semaphore is released... Now FreeRTOS detects a task wating for the semaphore and releases it, T2 enters ready state.
4. T4 maintains the processor. Feeding data to a DAC.
5. T4 goes to sleep, antoher task T2B becomes active.
6. T4 resumes with stage 1.

Now T2 once again runs during the read or during the sleep, just to detect that the semaphore is taken by T4.

Frankly I don't know how to get around this, since if I understand FreeRTOS a task waiting for a semaphore is not guaranteed to receive it. I susspose I could write a different way of handling semaphores... But it would be nice to have some input on how you would solve such a problem??

// Q

RE: Semaphores again

Posted by Nobody/Anonymous on December 19, 2005
Not exactly sure what the problem is here:

> The setup:
> 2 tasks, one running at prio 4, the other at 2. he high prio task is used for
> MP3-playback and basically only releases the CPU for 1 mS every 10-12 mS.

Ok.


> The two tasks share a common resource, an SPI bus which is used to communicate
> with a memory card and a display.

How is the SPI bus accessed? Directly by each task? If so does the semaphore remain unavailable until the entire message has been transmitted on the SPI bus?

.... Or, alternatively ....

is data being sent to the SPI queued for transmission, with the SPI interrupt used to send the next message in the queue. This way the semaphore only has to remain unavailable while data is being placed in the queue (if the data is atomic this will be handled by the queue mechanism and maybe the semaphore is not required at all?).


> What happens??
> Well, the SPI driver is called from two different tasks.. At the entry of the
> read and write functions the driver tries to aquire a semaphore. As it turns
> out the low prio task sometimes misses to aquire the semaphore, even though
> only 2-5 mS of it's allowed waiting time has passed.
>
> The reason I firgure is this... (In the following T# notation is used, # indicates
> the priority of the task).
>
> 1. T4 aquire the semaphore. Starts to read some data. During the read the processor
> is released, so that lower prio tasks can be run.

Hmm. Does not sound like a good idea. Do you really want your highest priority task yielding while it has a lock?

> 2. T2 runs, and tries to aquire the semaphore.. I has to wait.

Yep - locked out by the higher priority task.

> 3. T4, read is complete and the semaphore is released... Now FreeRTOS detects
> a task wating for the semaphore and releases it, T2 enters ready state.

Correct. T2 will be readied but won't run until it is the highest priority task in the system that is able to run.


> 4. T4 maintains the processor. Feeding data to a DAC.
> 5. T4 goes to sleep, antoher task T2B becomes active.

T2 will be at the back of the queue of tasks of priority 2 as it was the last to be put into the ready state, so T2B will run before it if it has not done so already.


> 6. T4 resumes with stage 1.
>
> Now T2 once again runs during the read or during the sleep, just to detect that
> the semaphore is taken by T4.
>
> Frankly I don't know how to get around this, since if I understand FreeRTOS
> a task waiting for a semaphore is not guaranteed to receive it. I susspose I
> could write a different way of handling semaphores... But it would be nice to
> have some input on how you would solve such a problem??


Sound like an application design issue rather than an RTOS issue as your description is as per the expected behaviour. I think you have to consider the design of your drivers and the prioritisation of your tasks.

Consider writing the driver so the semaphore is removed altogether. If the queue mechanism is used then the mutual exclusion to the hardware is handled by the queue. You might like to take a look at the i2c driver in the Wiznet demo for ideas.

RE: Semaphores again

Posted by Nobody/Anonymous on December 20, 2005
Thanks for the reply! You have cleared any question marks I've had. And I agree, from a design point of view it's not good to have multiple tasks with variating priorites as it will undoubtly lead to priority inversion(if nothing else ;). But there still must be cases when that is the way one have to go? or that a big no no? I've got a feeling that with MS Windows when releasing a semaphore and another task is wating for it, the ownership is transfered to the wating task immediatly? I think even the UNI OS NachOS(pain in the butt) does that. But have to look in to that at some time.

// Q

RE: Semaphores again

Posted by Jeff Smith on December 29, 2005
Well, I think the best solution is in consolidating actual SPI access to one task.

If T4 were the only task physically accessing SPI, you could have T2 send messages to another queue which is processed by T4. I haven't considered what exactly your T2 is doing with SPI, but in most cases I can see it working the way I described.


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