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New computer architecture for RTOS

Posted by Karl on December 20, 2009
Use of multiple memories minimizes clock cycles to execute C statements and expressions. The design is being implemented in a software emulator that produces a cycle log showing the flow of variables.
Here's an opportunity to help hone the RTOS timing since the registers won't have to be stacked, only the controls.
The interrupt mechanism has not yet been designed. The architecture can be tuned to RTOS functions.

RE: New computer architecture for RTOS

Posted by Dave on December 20, 2009
No idea what you are doing, saying, wanting or asking.

RE: New computer architecture for RTOS

Posted by Karl on December 20, 2009
Sorry, when I tried to preview, nothing happened. Then I could not delete the mistake. Now I see the preview is real time, but I still don't know how to recover.

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