Quality RTOS & Embedded Software

 Real time embedded FreeRTOS RSS feed 
Quick Start Supported MCUs PDF Books Trace Tools Ecosystem


Cortex M0+ tickless support

Posted by nurichard on December 16, 2013


I am looking to use FreeRTOS's tickless mode on a Cortex-M0+ core in the Freescale Kinetis KL series microcontroller.

As far as I can tell, the latest version of FreeRTOS (v7.6.0) does not officially support tickless for a Cortex M0 (or M0+). There is a short thread that suggests it may be possible.

Does anyone have / know of a code submission that is publicly available to assist with implementing tickless sleep on the KL parts?

My thanks for any guidance you can provide, Richard

Cortex M0+ tickless support

Posted by xz8987f on December 16, 2013

Hi Richard,

I have it implemented for Kinetis, see

http://mcuoneclipse.com/2013/07/06/low-power-with-freertos-tickless-idle-mod e/

Code is available on GitHub, see




alternate (5435 bytes)

Cortex M0+ tickless support

Posted by rtel on December 16, 2013

Thanks Erich - I really should link to that.

Richard - note the ability to manage time when the tick is stopped is built into the RTOS core source files itself, but actually managing clocks when the tick is stopped always requires some porting to specific chips. In other words, the port layer uses the functionality built into the core code to enable tickless operation. So while the FreeRTOS download does not provide an example 'off the shelf' (although Erich does) you can add tickless operation to almost any port with a little effort.

There are two ways of doing this. The first is to provide a generic implementation that does whatever the M0+ core allows you to do - but that will always be limited in effectiveness because the core is just the core, whereas power is consumed by peripherals, and because the clocks used to keep the timer counting in the core will stop if you sleep too deeply. Therefore for optimal low power you have to look outside of the core and into the IP the chip vendor (Freescale in your case) have provided for you. You should find the FreeRTOS implementation allows you to override the default timer configuration so you can provide your own, which will optimally be from a very slow (32KHz is popular) 32-bit timer that keeps running even when the clock feeding the M0+ core is off. There are three such examples of this type of optimisation on the FreeRTOS website (actually there are two, but another in SVN which will be on the website soon), and presumably Erich's provides another example that is happily specific to your selected chip.


Cortex M0+ tickless support

Posted by nurichard on December 17, 2013

Thank you both for your help.

Best regards, Richard

Cortex M0+ tickless support

Posted by kamab on March 4, 2014

As a follow up,

It seems like the m0 port did support tickless mode in 7.5.2 (allowed for ~SetupTimerInterrupt to be overridden and had hooks for Tickless Idle), but it stopped being supported in 7.6 and 8.0. Besides what you have mentioned, what made it change in that direction?

We are interesting in using the m0 port in a commercial application, but would likely need tickless mode for it to be viable. Just trying to explore potential problems.

Also, if we were to modify the m0 port, where/how would we be required to publish our source code? I apologize for the license question, I'm just a bit new to this stuff.

Cheers, Ben

Cortex M0+ tickless support

Posted by rtel on March 4, 2014

I've just compared version 7.5.2 of Source/Portable/GCC/ARM_CM0/port.c with version 8 of the same file and, while there have been many improvements between the two versions, I cannot see the change you are commenting on. The CM0 port never had built in tickless support, although (as per the thread above) it should be simple enough to add in (probably just by copying the functions out of the CM3/CM4 port layer).

Is your post related to the official FreeRTOS distribution or to Erich's slightly modified version?


[ Back to the top ]    [ About FreeRTOS ]    [ Privacy ]    [ Sitemap ]    [ ]

Copyright (C) Amazon Web Services, Inc. or its affiliates. All rights reserved.

Latest News

NXP tweet showing LPC5500 (ARMv8-M Cortex-M33) running FreeRTOS.

Version 10.1.1 of the FreeRTOS kernel is available for immediate download. MIT licensed.

View a recording of the "OTA Update Security and Reliability" webinar, presented by TI and AWS.


FreeRTOS and other embedded software careers at AWS.

FreeRTOS Partners

ARM Connected RTOS partner for all ARM microcontroller cores

Espressif ESP32

IAR Partner

Microchip Premier RTOS Partner

RTOS partner of NXP for all NXP ARM microcontrollers


STMicro RTOS partner supporting ARM7, ARM Cortex-M3, ARM Cortex-M4 and ARM Cortex-M0

Texas Instruments MCU Developer Network RTOS partner for ARM and MSP430 microcontrollers

OpenRTOS and SafeRTOS

Xilinx Microblaze and Zynq partner