I would like to know how to check if CPU is in IRQ handler routine. I see from technical reference manual that there is CPSR register which has 8 bit reserved for specifying current cpu mode but unfortunately in FreeRTOS CortexA9 port FreeRTOSIRQHandler I can see that during IRQ handling cpu mode is being switched to Supervisor mode hence there is no possibility to use CPSR. Any ideas how to work out this problem ?
Temporarily I turned off switching to SVC mode during IRQ handling but I suspect this is not good idea..
Thanks in advance
I'm sure there will be a way, but I would have to get the A9
architecture manual out to see, and I think you would need to look at
the GIC (interrupt controller) registers, not the CPU registers. I'm
pretty sure from memory there is a GIC register that tells you the
priority you are running at. As a quick and dirty solution, as there is
a single IRQ entry point, you could edit the IRQ entry code to increment
an interrupt nesting count on entry and decrement the count on exit -
then if the count is greater than 0 you know you are in the IRQ.
If you don't switch to SVC mode then the system will crash if interrupts
Answering my own question:
Richard you were right, there are RPR and IAR registers in GIC which give enough information to know if we are in IRQ or not. Thank you for hint !
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