Missing initialization of the Cortex-M0 SysTick register on FreeRTOS v.7.8.0

I’m using FreeRTOS since 7.4.0 and since then I have to add to every update the initialization of the systick register on "port.c" file from the "/Source/portable/GCC/ARMCM0/" folder. The problem is that the code initialize the portNVICSYSTICKLOAD with the calculated clock value, but after that line not initializes the portNVICSYSTICK_VAL to 0. It causes a start-up random delay of the first tick, because the we have to wait the transition from 1->0 from a counter that have a random number. Remember that the value of this register after a reset is: Unknown. On a speedy hardware’s this is not important but in battery designs with low frequency clocks this matter. The patch is very simple, on "/Source/portable/GCC/ARM_CM0/port.c" add: Add the definition of the register:
#define portNVICSYSTICKCTRL ( ( volatile uint32t *) 0xe000e010 ) #define portNVICSYSTICKLOAD ( ( volatile uint32t *) 0xe000e014 ) #define portNVICSYSTICKVAL ( ( volatile uint32t *) 0xe000e018 ) // <– new line #define portNVICINTCTRL ( ( volatile uint32t *) 0xe000ed04 ) #define portNVICSYSPRI2 ( ( volatile uint32t *) 0xe000ed20 )
Add the initialization of the register to zero:
/* Configure SysTick to interrupt at the requested rate. */ *(portNVICSYSTICKLOAD) = ( configCPUCLOCKHZ / configTICKRATEHZ ) – 1UL; *(portNVICSYSTICKVAL) = 0; // <– new line *(portNVICSYSTICKCTRL) = portNVICSYSTICKCLK | portNVICSYSTICKINT | portNVICSYSTICKENABLE;

Missing initialization of the Cortex-M0 SysTick register on FreeRTOS v.7.8.0

Thanks for the info, we will investigate this asap. Regards.