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M7 r0p1 port

Posted by cman12345 on January 26, 2016

Hi,

I was trying to find out more information about what M7 errata the pendSV handler is working around. I couldn't locate the errata doc and was hoping someone could point me to it. For reference I was looking at the "Errata workaround" lines below. Thanks!

~~~~ void xPortPendSVHandler( void ) { /* This is a naked function. */

__asm volatile
(
"	mrs r0, psp							\n"
"	isb									\n"
"										\n"
"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
"	ldr	r2, [r3]						\n"
"										\n"
"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
"	it eq								\n"
"	vstmdbeq r0!, {s16-s31}				\n"
"										\n"
"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
"										\n"
"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
"										\n"
"	stmdb sp!, {r3}						\n"
"	mov r0, %0 							\n"
"	cpsid i								\n" /* Errata workaround. */
"	msr basepri, r0						\n"
"	dsb									\n"
"   isb									\n"
"	cpsie i								\n" /* Errata workaround. */
[...]

~~~~


M7 r0p1 port

Posted by rtel on January 26, 2016

This was something found by our testing. As I recall (?) the basepri update does not take effect immediately, and it was necessary to place the "cpsid i" "cpsie i" instructions around the update to basepri to ensure modifying its value has an effect by the end of the isb instruction. You will find those additional asm instructions are the only difference between the M7r0p1 port and the standard M4F port.

Regards.


M7 r0p1 port

Posted by cman12345 on January 26, 2016

Ok, thanks for the info!


M7 r0p1 port

Posted by davidlcamlin on September 7, 2017

Hello, on SAME70Q21 (r0p1) still noticing occasional issues between 2 threads that use GiveFromISR and they get stuck in vListInsert loop on FreeRTOS v9.0.0. I also tried the v9.0.1 port.c and portmacro.h that add some barriers, but they still happen. Is errata workaround not needed inside vPortSetBASEPRI (called from portENABLEINTERRUPTS)? portFORCEINLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); }


M7 r0p1 port

Posted by davidlcamlin on September 7, 2017

Also there are 2 instructions "msr basepri, r0" in xPortPendSVHandler, maybe move the "cpsie i" after last one?


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