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wrong clock value in uIP_Demo_IAR_ARM7?

Posted by Tonau on July 28, 2009
Hi all,
i found a value off 47923200 for configCPU_CLOCK_HZ. But i think it must be 48054841.
Here is the calculation taken from James P. Lynchs AT91SAM7 Serial Communications:
MAINCK = 18432000 Hz crystal frequency
DIV = 14 (set up in lowlevelinit.c)
MUL = 72 (set up in lowlevelinit.c)
PLLCK = (MAINCK / DIV) * (MUL + 1) = 18432000/14 * (72 + 1) (phase lock loop clock)
PLLCLK = 1316571 * 73 = 96109683 Hz
MCK = PLLCLK / 2 = 96109683 / 2 = 48054841 Hz (main clock MCK)
This calculation rounds after every step of calculation. I think this is right if only integer values are used by the SAM7X to calculate the PLLCLK.
So what value is the right one? Has anyone a calculation with 47923200 as result?

Thanks!

RE: wrong clock value in uIP_Demo_IAR_ARM7?

Posted by mike on July 28, 2009
This is the value from using DIV 5 and MUL 25, which is sometimes used.
Some users seem to think this is more certain to start up, but gives an error of 0.16% from the ideal 48MHz (compared with 0.11% for the 14/72 values).
Regards

RE: wrong clock value in uIP_Demo_IAR_ARM7?

Posted by Tonau on July 28, 2009
Thanks for your fast response.
I think I will use DIV = 14 and MUL = 72 values because of the lower error. So I change the configCPU_CLOCK_HZ to 48054841.

Regards.

RE: wrong clock value in uIP_Demo_IAR_ARM7?

Posted by Adam Turowski on July 28, 2009
You can easily achieve ideal 48MHz clock for AT91SAM7X when using 18.432MHz crystal. I believe that this setup is used by SAM-BA bootloader. Here is some code:

/* Main oscillator */
MAIN_OSC_STARTUP_TIME = 64 /* main oscilator startup time in slow clock cycles divided by 8 */

/* setup PLL to generate 192MHz frequency using 18.432MHz crystal */
/* 18.432MHz/24*125 = 96MHz. USB clock will be 96MHz/2=48MHz. MCK clock will be 96MHz/2=48MHz */
USBDIV_VAL = AT91C_CKGR_USBDIV_2 /* USBDIV field value in CKGR_PLLR register. USB frequency will be PLL freq divider by 4 */
PLL_MUL_VAL = (((125-1) << 16) & AT91C_CKGR_MUL)/* MUL field value in CKGR_PLLR register. Actual multipier for PLL will be equal to this field value plus 1 */
PLL_DIV_VAL = ((24 << 0) & AT91C_CKGR_DIV) /* DIV field value in CKGR_PLLR register. */
PLL_OUT_VAL = AT91C_CKGR_OUT_0 /* OUT field value in CKGR_PLLR register. It is selected for 96MHz PLL out freq */
PLLCOUNT_VAL = ((45 << 8) & AT91C_CKGR_PLLCOUNT) /* waiting for PLL lock time in slow clock period units */

Using this values I've never had an issue with startup.

Hope that helps,
Adam

RE: wrong clock value in uIP_Demo_IAR_ARM7?

Posted by Adam Turowski on July 28, 2009
Oops. There is a typo in comment. Correct comment should be /* USBDIV field value in CKGR_PLLR register. USB frequency will be PLL freq divider by 2 */

RE: wrong clock value in uIP_Demo_IAR_ARM7?

Posted by Tonau on July 29, 2009
Hi Adam,

thanks for your suggestion. I think the USBDIV_VAL = AT91C_CKGR_USBDIV_2 must also be changed to AT91C_CKGR_USBDIV_1. See AT91SAM7X256.h:

#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4

I tested your values except usbtraffic and it worked fine for me.
Thanks a lot!
Tobias

RE: wrong clock value in uIP_Demo_IAR_ARM7?

Posted by Tonau on July 29, 2009
Hi,
now I found why this is not the standard configuration. Also it seems to work good, now we work with a input frequency lower than the minimum allowed frequency.
DIV = 24 -> f_in = 768 kHz
f_min = 1MHz
So I'm not shure it is a good idea to use this values.

Best regards,
Tobias

RE: wrong clock value in uIP_Demo_IAR_ARM7?

Posted by Adam Turowski on July 29, 2009
Hi Tobias,
You are totally right. I found this some time ago and by accident I've provided you with old repository code. Sorry for that.

The correct formula is:
(18.432MHz/12)*125/4=48MHz
So DIV should be 12, MUL field should be (125-1) =124 and MCK and USB clock dividers should be set to divide by 4 to have ideal 48MHz.

Once again sorry for confussion.

Best ragards,
Adam


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