Hard Faults in Cortex M3 on unaligned access
Posted by Doug Bailey
on June 8, 2011
I am using FreeRTOS V6.1.0 running on a NXP LPC1758 processor (ARM Cortex M3) and compiled using Code Red's LPCxpresso development suite. This uses a toolchain based on GCC V4.4.1.
I have been able to integrate FreeRTOS into my application and all works fine except when I enable the UNALIGN_TRP bit in the System Control Block's Configuration Control Register. This bit enables unaligned access traps as noted in the NXP LPC1758 tech reference (126.96.36.199 Configuration and Control Register).
Enables unaligned access traps:
0 = do not trap unaligned halfword and word accesses
1 = trap unaligned halfword and word accesses.
If this bit is set to 1, an unaligned access generates a usage fault.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of whether UNALIGN_TRP is set to 1.
When I enable this bit, I get Hard Fault exceptions at different times in the operation. It appears that they occur within the kernel though the location is not always consistent.
When I disable the bit, I see no anomalous behavior and all seems to works as I expect it.
Is this a known issue for the Cortex M3 port? Any suggestions about how to handle it apart from disabling the bit?
RE: Hard Faults in Cortex M3 on unaligned access
Posted by MEdwards
on June 8, 2011
I don't think I have ever enabled that bit so can't say if it is normal. The compiler should ensure everything is aligned. The place where the kernel could get it wrong (but doesn't, at least not in the latest versions) is when the stack is allocated. This should be on an 8 byte boundary. You could check that (check the stack pointer in the task). You could also get a problem if you are packing structures, either explicitly or with a compiler flag. That is something that is often done in protocols such as TCP/IP.
Copyright (C) Amazon Web Services, Inc. or its affiliates. All rights reserved.