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Potential tick speedup

Posted by Robert Turner on June 15, 2011
Hi,
I've been looking at the possibility of only performing a context switch within a tick (preemptive only of course) if there's other same-priority tasks ready to be executed. I often find in my projects that most tasks spend their time blocked with only one or two needing a lot of processing time (multiple ticks).
At present a tick first saves the context, selects the next highest priority task and then restores the context. In ports where the context saving/restoring is expensive, or say, for the ARM_CM3 ports where a tick consists of two interrupt calls (first SysTick and then PendSVC), could we first check the list of running tasks if there is a new task to be switched to? This could then prevent the context saving/restoring (and the PendSVC interrupt for ARM_CM3 port) if there are no other tasks waiting.
Thoughts?

RE: Potential tick speedup

Posted by Richard on June 15, 2011
I have often thought about how that can be optimised, but there are a few problems to overcome:

1) There are lots of different mechanisms for instigating and performing a context switch. You have identified two already in your post. You have to come up with a solution that works for all.

2) What you are wanting to do is add code by having an extra check. This will increase the context switch time when one is required. Especially when you have to do things like check delayed lists, etc. The result may be that the modification is much less efficient than the existing code.

3) What are you going to do if the extra check decides a context switch is required? For example, on an ARM7, if you enter the tick interrupt using an interrupt stack frame, decide a context switch is required, how are you going to save the task context (which has been modified by the addition of an interrupt stack frame) without exiting and re-entering a different interrupt. There are ways around that, but not without increasing the stack usage. That is more problematic in some ports than others, for example, more complex architectures and more complex ports use a separate interrupt stack.

These are not absolute points - more of a brain storm.

Regards.


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