results in an ASSERT fail at: portASSERTIFINTERRUPTPRIORITYINVALID(); Secondly, if I skip the XSCUGICBINPTOFFSET write and just insert the two functions, XilEnableNestInterrupts() and XilDisableNestInterrupts() in my interrupt handler(s) as instructed my program crashes at taskEXITCRITICAL() in xTaskResumeAll() after the very first interrupt handler call. Note the the scugic driver html doc contains the comment: Nested interrupts are not supported by this driver Am I going about this the right way? I would VERY MUCH like to have this feature working and would greatly appreciate any help at all.
XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_BIN_PT_OFFSET, 0x03);
soc: XC7Z020 with dual cortexA9 (Trenz TE0720) sdk: 2017.2 os: FreeRTOS 9.0 interrupt driver: scugicv37 My system is running well (single core) with several interrupts but without interrupt nesting (pre-emption). My two highest priority interrupts are running at priority 18 (TTC) and 19 (axidma). I would very much like nested interrupt handling to work so that the timer interrupt could pre-empt the dma interrupt (as well as all the other lower priority interrupts). In searching for a solution the closest I’ve come is from 2014: https://www.xilinx.com/support/answers/54128.html Unfortunately this solution does not work for me and leads to problems. First of all, the addition of the following line (as instructed):
Sorry for brief reply at this time – but FreeRTOS manages the interrupts so I shouldn’t get too distracted by Xilinx docs unless they are specific to their FreeRTOS BSP. The Zynq demo in the FreeRTOS kernel download includes interrupt nesting tests so perhaps you could use those as a reference for how to set this up. Look at the “IntQTimer” files which configures different timers at different interrupt priorities.
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