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AT91SAM7S-EK board questions

Posted by Nobody/Anonymous on March 14, 2006
Hi,

I am new to both ARM and FreeRTOS so please bear with me. The devel environment is IAR 4.11A kickstart edition, which from forum searching appears to 4.20 format. Sure enough FreeRTOS 3.2.4 project does not open up so using FreeRTOS 3.2.1

There are 2 options in configuration Flash Debug and Flash Bin. Atmel AT91SAM7S64 has a bug in there which only allows 'reliable' flashing for abt 100 times. So I dont want to burn to flash. Is there a way I can produce "RAM Debug" version? I tried "New config" but there are no good options to base from. Sorry, this question might be good on IAR forum.

Also, will things fit into the 32KB limit imposed by kickstart edition?

Thanks
Nihar




RE: AT91SAM7S-EK board questions

Posted by Nobody/Anonymous on March 14, 2006
> I am new to both ARM and FreeRTOS so please bear with me. The devel environment
> is IAR 4.11A kickstart edition, which from forum searching appears to 4.20 format.
> Sure enough FreeRTOS 3.2.4 project does not open up so using FreeRTOS 3.2.1


Can you not update your version from the IAR WEB site. I think you can download updates. If you are using the KickStart version then you can just download the latest.

> There are 2 options in configuration Flash Debug and Flash Bin. Atmel AT91SAM7S64
> has a bug in there which only allows 'reliable' flashing for abt 100 times.

Wow, I never new that.

> So I dont want to burn to flash. Is there a way I can produce "RAM Debug" version?
> I tried "New config" but there are no good options to base from. Sorry, this
> question might be good on IAR forum.


This might just be a case of redefining the linker script so code goes to RAM (this is how the GCC demo works) but really is 16K RAM enough for both your application and the code?


> Also, will things fit into the 32KB limit imposed by kickstart edition?

Depends on what you are doing. The uIP demo (SAM7X) runs with the KickStart version.

RE: AT91SAM7S-EK board questions

Posted by Nobody/Anonymous on March 14, 2006
Yes, I did update from the website but it only patched some parts of the code. We also had received some patch from IAR for a SPI interrupt bug and I am not yet ready to monkey around with the code I have inherited.


MY BAD!!!
We just inherited a system which uses the ARM processor from our now "former" employee and he told me that there is a bug which allows only 100 times flash writes. I should have personally checked the data sheet. Its not for the flash, only the NVM

From the errata...
**************************************
NVM Bits: Write/Erase Cycles Number
The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
This maximum number of write/erase cycles is not applicable to 64 KB Flash memory, it remains
at10K for the Flash memory.


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