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portCRITICAL_NESTING_IN_TCB

Posted by ulixxe on March 15, 2010
I did a port on plasma mcu (MIPS I instruction set from opencores.com).
I made it by merging demos from PIC32 and ARM CM3. I implemented both configKERNEL_INTERRUPT_PRIORITY and configMAX_SYSCALL_INTERRUPT_PRIORITY. But a difference about the two port is than PIC32 uses portCRITICAL_NESTING_IN_TCB=1 whereas ARM-CM3 uses a global static uxInterruptNesting variable, so my question is why to use portCRITICAL_NESTING_IN_TCB=1? Indeed it uses more RAM to store uxInterruptNesting for each task. What is its benefit?
Thank in advance
Santo

RE: portCRITICAL_NESTING_IN_TCB

Posted by Richard on March 15, 2010
The Cortex M3 is a bit unique in that a context switch will only occur when the critical nesting count is zero. Most ports (all other ports?) store a critical nesting count per task. Whether this is stored in the TCB or task stack does not make a difference to the amount of RAM required. Storing it in the TCB is much simpler (less context switch code) but can also be less flexible and less efficient - so it really depends on the architecture.

It would be great if you uploaded your port to the new FreeRTOS Interactive forums.
http://interactive.freertos.org

Regards.


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