Some of my team have been questioning how thread safe the *fromISR() functions are.
Currently we use these lightweight API calls in some module interfaces in the case that they are called from high priority interrupts.
They also referenced examples 1 and 2 from the lightweight API section here:
Although these examples seem to be legacy code (Version 4.8 ~ ). It does mention
"We have done nothing between Listing 1 and Listing 2 to ensure interrupt safety. This is therefore still not appropriate usage if the queue is also accessed from an ISR."
That said, the third example (using the return value to indicate an opportunity to yield) seems to be up to date. And a quick look into the functions save & disable interrupts on entry then restore the register status on exit, which prevents further interrupts. However there is also a critical section in this example placed around the *fromISR() function.
1. Is this third example thread safe? Can it be called from an ISR without the need to create a critical section or manage the thread interactions between queue resources?
I see no reason that the *fromISR() functions cannot be called from tasks as well, just the yield behaviour needs to be managed by the application designer.
2. Is it true that the main difference between the *fromISR() function and the normal API is the control over the yield?
The main reason I would like to do this is for the purpose of re-usability in application code. Having different functions based on whether the queue is being added to from an ISR or a low prio task adds to redundancy, or the need to create wrappers.
Is that page still linked into the website? Did you find it from a link
on a different page?
Whether the 'FromISR' functions are thread safe or not depends on the
port you are using. As general rule, if the port supports interrupt
nesting then the functions are thread safe because they implement their
own critical sections. if the port doesn't support interrupt nesting
then the 'FromISR' functions will not have critical sections and will
not be thread safe.
I am afraid I don't know if it is still linked to a website. Someone had sent me the link to check over as they had concerns about this. Our port is to SAMD20 ARM Cortex M0+. Which supports nested interrupts.
But all the same it might be wise to protect our fromISR functions with critical sections for portability.
Do you think this might have any undesired behaviour?
The M0 port, unlike the M3, M4 and M7 ports, does not support interrupt nesting. All the other 'M' cores have a basepri reg, but the M0 does not.
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