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Supervisor Stack usage in Interrupt Service Routine on Cortex A9

Posted by pixt on March 6, 2017

Hello,

I am using a Xilinx Zynq-7000 (ARM Cortex A9) with FreeRTOS. I recently had the problem that my interrupt service routine wrote into memory regions it was not supposed to due to a stack overflow. The problem was not solved by only increasing the IRQ stack size in the linker script. I found out that the ISR was using the supervisor stack. After increasing the size of the supervisor stack the stack overflow disappeared. Can you explain to me why the ISR uses the supervisor stack and why it was neccessary to increase the size of the supervisor stack? Thank you.

Best regards, pixt


Supervisor Stack usage in Interrupt Service Routine on Cortex A9

Posted by richarddamon on March 6, 2017

The ARM architecture uses multiple stacks for different hardware levels of operation (traps, interrupts[fast, nested], system software interrupt, user programs), so you need to make room in the stack that will be used by that operation.On ARM architectures, FreeRTOS triggers a supervisor interrupt to do the context switch between tasks.


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