I asked William about this (William is the NIOS man), and this is his response:
I think that the root of the problem is that the latest Altera tools have changed the way the system library is created. The ‘syslib’ project is now called ‘BSP’ and requires a different file to generate the necessary hardware description for the software. Therefore, I think that the ‘ptf’ has been deprecated, or at the very least, it cannot be used by the Nios environment.
When I tried to use the latest Altera software, I came across this problem but rolled back the Altera software because I didn’t have the FPGA project to generate the necessary files. In theory, you could use the latest Quartus to create the files because you have the FPGA design for the EBV DBC3C40 board.
More appropriately for ‘dsmhmm’, he just needs to do a find and replace of ‘SYS_CLK_’ to the name of his Timer peripheral in port.c. Replacing ‘SYS_CLK_’ will catch ‘SYS_CLK_BASE’, which is the memory mapped address of the peripheral, and ‘SYS_CLK_IRQ’, which is the IRQ number.
I am not 100% sure about the new format mainly because I haven’t tried it but at the very least ‘dsmhmm’ will know which lines need to be changed in the port layer code.