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Use of barriers when setting BASEPRI on Cortex M7

Posted by kostas2010 on May 17, 2017

Raising BASEPRI on M7 port (v9.0.0) is done as below: ~~~

define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI()

static portFORCE_INLINE void vPortRaiseBASEPRI( void )

{

uint32t ulNewBASEPRI = configMAXSYSCALLINTERRUPTPRIORITY;

__asm

{

	/* Set BASEPRI to the max syscall priority to effect a critical

	section. */

	cpsid i

	msr basepri, ulNewBASEPRI

	dsb

	isb

	cpsie i

}

}

~~~ Could you explain the need for a DSB?

Additionally, I understand that ISB is used to ensure that when this function returns, the BASEPRI change is observed. However this makes sense only if ISB is placed after "cpsie i" instruction so that the PRIMASK clear is also observed.

I have also looked into this (http://infocenter.arm.com/help/topic/com.arm.doc.dai0321a/DAI0321Aprogrammingguidememorybarriersform_profile.pdf) but I could not find the exact case in the guidelines.


Use of barriers when setting BASEPRI on Cortex M7

Posted by rtel on May 17, 2017

The cpsid/cpsie instructions are a workaround to a silicon errata and are only required if the revision of the core is r01p, otherwise use the Cortex-M4F port layer. I imagine the errata docs will be the only place they are mentioned.


Use of barriers when setting BASEPRI on Cortex M7

Posted by kostas2010 on May 18, 2017

Thank you for your answer.

What about the need for DSB? Is it required after the MSR instruction that sets BASEPRI?

(To help our discussion I am pasting the CM4F port that is suitable for our CM7 (non r0p1))

~~~ static portFORCEINLINE void vPortRaiseBASEPRI( void ) { uint32t ulNewBASEPRI = configMAXSYSCALLINTERRUPT_PRIORITY;

__asm
{
	/* Set BASEPRI to the max syscall priority to effect a critical
	section. */
	msr basepri, ulNewBASEPRI
	dsb
	isb
}

} ~~~


Use of barriers when setting BASEPRI on Cortex M7

Posted by rtel on May 18, 2017

On the M3 and M4 it is actually after the next instruction: "MSR side-effects are visible after one further instruction is executed". I believe it is different on the M7 though and will have to look it up. The M4F port was updated so it could also be used on an M7.


Use of barriers when setting BASEPRI on Cortex M7

Posted by kostas2010 on May 19, 2017

So, for M3/4 at least, removing the DSB instruction means that the side-effects will be visible after the ISB instruction, which is what we want. So it looks that practically there is no need for a DSB.

I will be waiting for your findings on M7 as well. Many thanks again for the help.


Use of barriers when setting BASEPRI on Cortex M7

Posted by kostas2010 on May 24, 2017

Any news on this?


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