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Cortex-M4 MPU support

Posted by dumarjo on November 6, 2013

Hi,

I see in the source that the cortex-M3 MPU is supported. Is there a M4 MPU too ?

I don't see anything about the M4

Regards

Jonathan


Cortex-M4 MPU support

Posted by richardbarry on November 6, 2013

There is no specific M4 version of the MPU code, but there are few differences between the M3 and M4 code so just creating one using the M3 version as a starting point would not be tricky.

If you M4 does not have an FPU, or you leave the FPU switched off, then you can use the M3 port anyway.

Regards.


Cortex-M4 MPU support

Posted by dumarjo on November 6, 2013

Hi Richard,

Le 2013-11-06 10:21, Richard a écrit : > > There is no specific M4 version of the MPU code, but there are few > differences between the M3 and M4 code so just creating one using the > M3 version as a starting point would not be tricky. > > If you M4 does not have an FPU, or you leave the FPU switched off, > then you can use the M3 port anyway. > I use the FPU too. I would take a look at the M3 port vs the M4 port and give it a try !

regards

Jonathan


Cortex-M4 MPU support

Posted by hawk777 on November 7, 2013

A diff between CM3 and CM4F is very very small, and I expect will apply quite easily to the CM3MPU tree (don’t try it the other way). That’s what I plan to do to use FreeRTOS, until an official release for CM4FMPU shows up (if it does).


Cortex-M4 MPU support

Posted by dumarjo on November 7, 2013

Hi,

Le 2013-11-07 00:24, Christopher Head a écrit : > > A diff between CM3 and CM4F is very very small, and I expect will > apply quite easily to the CM3MPU tree (don’t try it the other way). > That’s what I plan to do to use FreeRTOS, until an official release > for CM4FMPU shows up (if it does). > I just found a sample of code in the interactive forum. I have adapted it to the 7.5.3 (original was for 7.4.0). I will test it today. If it work, I will try to generate patches and send it to Richard.

Regards

Jonathan > ------------------------------------------------------------------------ > > Cortex-M4 MPU support > https://sourceforge.net/p/freertos/discussion/382005/thread/31cba9a5/?limit=25#182e > > ------------------------------------------------------------------------ > > Sent from sourceforge.net because you indicated interest in > https://sourceforge.net/p/freertos/discussion/382005/ > > To unsubscribe from further messages, please visit > https://sourceforge.net/auth/subscriptions/ > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner http://www.mailscanner.info/, and is > believed to be clean.


Cortex-M4 MPU support

Posted by dumarjo on November 8, 2013

Hi,

Le 2013-11-06 10:21, Richard a écrit : > > There is no specific M4 version of the MPU code, but there are few > differences between the M3 and M4 code so just creating one using the > M3 version as a starting point would not be tricky. > I did the merge and everything seem to work.

I have a quastion about the mpu. I hope someone here can give me some hint.

I have setup 2 tasks in user mode. As soon as I do a malloc like this.

char *p = (char *)pvPortMalloc(256);

 p[0] = 0x55; <---- trig the memmanage fault.

If my tasks are in priveleged mode, no probleme at all.

From what I understand, the full RAM is supposed to be accible in R/W by default. I have tweak my linker script based on the demos.

It it normal ?

Jonathan

If you M4 does not have an FPU, or you leave the FPU switched off, then you can use the M3 port anyway.

Regards.


Cortex-M4 MPU support https://sourceforge.net/p/freertos/discussion/382005/thread/31cba9a5/?limit=50#d7b4


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Cortex-M4 MPU support

Posted by richardbarry on November 8, 2013

By default, and unprivileged task only has access to its own stack, and nothing else. If you want it to access other RAM you have to explicitly tell the kernel it is ok. This can be done at the point the task is created, and then changed at run time.

http://www.freertos.org/xTaskCreateRestricted.html http://www.freertos.org/vTaskAllocateMPURegions.html

Regards.


Cortex-M4 MPU support

Posted by dumarjo on November 8, 2013

Hi,

Le 2013-11-08 09:31, Richard a écrit : > > By default, and unprivileged task only has access to its own stack, > and nothing else. If you want it to access other RAM you have to > explicitly tell the kernel it is ok. This can be done at the point the > task is created, and then changed at run time. > I was confused then. I see in the port.c in fonction vPortStoreTaskMPUSettings

 if( xRegions == NULL )
 {
     /* No MPU regions are specified so allow access to all RAM. */
     xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
             ( ( unsigned long ) __SRAM_segment_start__ ) | /* Base 

address. */ ( portMPUREGIONVALID ) | ( portSTACK_REGION );

     xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
             ( portMPU_REGION_READ_WRITE ) |
             ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
             ( prvGetMPURegionSizeSetting( ( unsigned long ) 

SRAMsegmentend - ( unsigned long ) SRAMsegmentstart ) ) | ( portMPUREGIONENABLE );

I thought that the full RAM was accessible.

Regards

Jonathan


Cortex-M4 MPU support

Posted by dumarjo on November 8, 2013

Hi,

Le 2013-11-08 09:31, Richard a écrit : > > By default, and unprivileged task only has access to its own stack, > and nothing else. If you want it to access other RAM you have to > explicitly tell the kernel it is ok. This can be done at the point the > task is created, and then changed at run time. > > http://www.freertos.org/xTaskCreateRestricted.html > http://www.freertos.org/vTaskAllocateMPURegions.html > > Regards. >

How do you handle dynamic memory allocation in a RTOS system with the MPU enabled ?

Regards

Jonathan


Cortex-M4 MPU support

Posted by dumarjo on November 22, 2013

Hi Richard,

I have read gain and again on the MPU And I have a question about the Port (for the M3). I see in the fonction prvSetupMPU, that you have anabled the Privielege Background with /* Enable the MPU with the background region configured. */ *portMPUCTRL |= ( portMPUENABLE | portMPUBACKGROUNDENABLE );

I wonder why you define explicitely privilege region for the kernel ? Should this be done directly by the portMPUBACKGROUNDENABLE ?

In a big application, How do you share Queue Handle, Mutex, etc... ?

Regards

Jonathan Le 2013-11-08 09:31, Richard a écrit : > > By default, and unprivileged task only has access to its own stack, > and nothing else. If you want it to access other RAM you have to > explicitly tell the kernel it is ok. This can be done at the point the > task is created, and then changed at run time. > > http://www.freertos.org/xTaskCreateRestricted.html > http://www.freertos.org/vTaskAllocateMPURegions.html > > Regards. > > ------------------------------------------------------------------------ > > Cortex-M4 MPU support > https://sourceforge.net/p/freertos/discussion/382005/thread/31cba9a5/?limit=50#127c > > ------------------------------------------------------------------------ > > Sent from sourceforge.net because you indicated interest in > https://sourceforge.net/p/freertos/discussion/382005/ > > To unsubscribe from further messages, please visit > https://sourceforge.net/auth/subscriptions/ > > > -- > This message has been scanned for viruses and > dangerous content by MailScanner http://www.mailscanner.info/, and is > believed to be clean.


Cortex-M4 MPU support

Posted by rtel on November 22, 2013

To be honest, I can't remember, it was a while ago it was developed. What happens if you turn the background region off?

Regards.


Cortex-M4 MPU support

Posted by dumarjo on November 22, 2013

Hi,

Le 2013-11-22 10:57, Real Time Engineers ltd. a écrit : > > To be honest, I can't remember, it was a while ago it was developed. > What happens if you turn the background region off? > Well I would like to test the opposit. I think we should use the background to privileged mode and not define the 2 region (flash and ram) privileged. Then this should give 2 more region to the task.

I try to do that but I got a problem in the context switch. Since we have more region, I think we chould change something in the contextswitch. Probably around those line

     "    ldr r1, [r3]                        \n"
     "    ldr r0, [r1]                        \n" /* The first item 

in the TCB is the task top of stack. / " add r1, r1, #4 n" / Move onto the second item in the TCB... / " ldr r2, =0xe000ed9c n" / Region Base Address register. / " ldmia r1!, {r4-r11} n" / Read 4 sets of MPU registers. / " stmia r2!, {r4-r11} n" / Write 4 sets of MPU registers. */

I'm not sure to understand this correctly.

Those instruction read 4 region from the xMPU_SETTINGS xMPUSettings;
and write thoses to 0xe000ed9c ?

Regards

Jonathan

Regards.


Cortex-M4 MPU support https://sourceforge.net/p/freertos/discussion/382005/thread/31cba9a5/?limit=25#fd56


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