RL78 and priority level of interrupt
Posted by frantzca
on October 26, 2011
I use Freertos with RL78 target and the compiler used is IAR. My Freertos configuration doesn’t use the preemption (configUSE_PREEMPTION == 0.
I’ve encountered some “jitter” problems with a timer interrup. This regular interrupt must be acknowledged in my application without this jitter. I have checked the reason of this jitter and I’ve seen that the macro taskYIELD() use the BRK instruction. The acknowledgement of this interrupt disables all interrupts (like DI), and my normal interruption is served only after each RETB instruction. ( For my test, I have got only one active task and this task is suspended by call of vTaskDelay() , so portYield() is called everytime)
Furthermore, the RL78 can have 4 levels of interruption.
My questions are as follows:
1) It is possible to introduce the concept of priority level and have the same behaviour as RX62N, with the 2 parameters?
2) Additionally and to avoid any problems with the interrupt being disabled in the main loop (in case there is none preemption option), is it possible to not disabled the global flag interrupt (as BRK instruction made) or retabish it ?
Thank you in advance for your answers.
RE: RL78 and priority level of interrupt
Posted by Richard
on October 26, 2011
These comments are made without having done any testing, so they are just ideas:
1) It may be possible to re-enable interrupts in the BRK handler to allow interrupts to nest provided the interrupts that do nest do not call any FreeRTOS API functions.
2) If you want nested interrupt to have access to the interrupt safe FreeRTOS API (the API functions that end in FromISR()), then you would have to change the ENTER/EXIT critical functions to mask off a subset of priorities only, maybe up to priority 2. You would also have to implement portSET_INTERRUPT_MASK_FROM_ISR() and portCLEAR_INTERRUPT_MASK_FROM_ISR() to do the same thing, with the SET macro returning the original interrupt priority, and the CLEAR macro restoring the original interrupt priority.
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