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Cortex IRQ priority issue?

Posted by gigglergigger on October 9, 2015

Hi,

I've enabled configASSERT macro in my app config and noticed FRTOS now complaining (asserting) due to interrupts having wrong POR priority. They are all 0.

System information: LPCXpresso v7.9.2 [Build 493] [2015-09-14] FreeRTOS V7.5.3 Cortex M3 (LPC1769) LPCOpen (no idea?) core_cm3 (v3.20, came with lpcopen)

Using IRQ's for I2C, CAN and UART.

From CMSIS:

_STATICINLINE void NVICSetPriority(IRQnType IRQn, uint32t priority) { if(IRQn < 0) { SCB->SHP[((uint32t)(IRQn) & 0xF)-4] = ((priority << (8 - _NVICPRIOBITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ else { NVIC->IP[(uint32t)(IRQn)] = ((priority << (8 - _NVICPRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ }

_STATICINLINE uint32t SysTickConfig(uint32t ticks) { if ((ticks - 1) > SysTickLOADRELOADMsk) return (1); /* Reload value impossible */

SysTick->LOAD = ticks - 1; /* set reload register / NVICSetPriority (SysTickIRQn, (1<<_NVICPRIO_BITS) - 1); / set Priority for Systick Interrupt / SysTick->VAL = 0; / Load the SysTick Counter Value / SysTick->CTRL = SysTickCTRLCLKSOURCEMsk | SysTickCTRLTICKINTMsk | SysTickCTRLENABLE_Msk; / Enable SysTick IRQ and SysTick Timer / return (0); / Function successful */ }

these are in my config:

configLIBRARYLOWESTINTERRUPTPRIORITY 0x1f configLIBRARYMAXSYSCALLINTERRUPT_PRIORITY 5

enum eIRQPRIORITY { eIRQPRIORITYI2C =configLIBRARYLOWESTINTERRUPTPRIORITY+0x03, // ISR does not invoke freeRTOS API eIRQPRIORITYCAN =configLIBRARYLOWESTINTERRUPTPRIORITY+0x02, eIRQPRIORITYUART =configLIBRARYLOWESTINTERRUPTPRIORITY+0x01, // highest for this application };

These are now my prioritys using CMSIS, like

NVICSetPriority(xIRQn, eIRQPRIORITYI2C);

Even on this forum there are people who in their posts are using low values for this function but I found I could not use anything lower than configLIBRARYLOWESTINTERRUPT_PRIORITY, if I do the interrupt is'nt serviced.

Originally I noticed every priority set to 0 (highest), so naturally I set them as follows:

NVICSetPriority(I2Cx, 3); // lowest does not matter NVICSetPriority(CANx, 2); NVIC_SetPriority(UARTx 1); // highest user IRQ (lower than system tick for OS)

But the above fails to generate interrupts.

When I look at the NVICSetPriority(...) it does the shifts internally (code above), so why do i have to put anything higher than 0x1f? The odd thing I found is SysTickConfig(...) which I am not using is in the same CMSIS header file, yet it shifts like what is done within the SetPriority call.

Why does this not work? NVIC_SetPriority(I2Cx, 3); // lowest does not matter

but this seems to? NVIC_SetPriority(I2Cx, 0x1f + 3); // lowest does not matter

Regards

dc


Cortex IRQ priority issue?

Posted by heinbali01 on October 10, 2015

I've read your post three times and it makes me doubt whether you are aware that "the higher the value, the lower the priority"?

So if configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY equals 5, and if I'm not mistaken :-), you can use values of 5 and higher.

Regards.


Cortex IRQ priority issue?

Posted by rtel on October 10, 2015

It is confusing, so there is a page that attempts to explain it: http://www.freertos.org/RTOS-Cortex-M3-M4.html


Cortex IRQ priority issue?

Posted by gigglergigger on October 10, 2015

Hi,

Thanks for reading my post, so many times!

I should have said; when I first noticed the issues I read that link with specifics for Cortex port, FRTOS.

I started with

configLIBRARYMAXSYSCALLINTERRUPTPRIORITY which is in my header files as 5

That does not work for me either and I get no I2C IRQ's so reading a byte polls a status bit forever so I started raising the values, i.e. lowering priority and only get IRQ's from I2C above 0x1f which made me go back to the config file for FRTOS and start looking for other macros related to IRQ's.

I have a product configuration read from serial flash over I2C before tasker is started, so I made sure I did not call from the I2C (module, including ISR) any FRTOS API. It's all handled as baremetal code. If I set a breakpoint on the IRQ handler for the I2C bus I am using, I only see interrupts at priority 0 (i.e. leaving it as POR) OR by calling NVIC_SetPriority(I2Cx, 0x1f + n)

I have also tried setting the priority group to 0 using the same CMSIS API - I know I don't need to for NXP/lpcopen only STM32 but what the hell.

There is an interesting comment in the default FRTOS header "FreeRTOSConfig.h" as distributed with openlpc samples:

/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ define configLIBRARYLOWESTINTERRUPT_PRIORITY 0x1f

To me, someone is specifically telling me when I want to change the IRQ priority, assuming using CMSIS, NVIC_SetPriority(...), for NXP under FRTOS I should not be setting it less than 0x1f. Is this correct?

It wasn't clear to me from reading the ARM reference manuals on Cortex priority setting and the FRTOS specifics on Cortex M3 (they don't mention (1<<5-1=0x1f) as minimum)+ other peoples posts on using the function (which maybe because they are using a diff ARM) why I had to use such a large priority (>=low priority)? Because of this I think perhaps something is an issue.

I picked my I2C code because its not using FRTOS API the same thing happens with CAN bus IRQ's set below 0x1f and they use the FRTOS API. I don't want to talk about them until I can clarify the priorty value using the NVIC function on my setup.

Regards,

dc


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