Quality RTOS & Embedded Software

 Real time embedded FreeRTOS RSS feed 
Quick Start Supported MCUs PDF Books Trace Tools Ecosystem


Interrupt Nesting

Posted by John W. on September 28, 2007
Hello Richard,

Will interrupt nesting be supported soon for all ports?

For the stack challenged like the 8051 it may not make much sense - but as a diagnostic tool it could be very helpful even
on the 8051.

John W.

RE: Interrupt Nesting

Posted by olibats on September 28, 2007

As far as I know about it, Interrupt Nesting has to be supported by the processor. Which means, if a given processor does not support Interrupt Nesting, than it is not possible to add it to its Port.

If any other given processor supports it, you have to give the tick-timer-isr and the portYIELD (if realized as SWI) a priority number while installing them.


RE: Interrupt Nesting

Posted by John W. on October 1, 2007

It'd be great if we could get a comment from you on this.


RE: Interrupt Nesting

Posted by Richard on October 2, 2007
My preference is not to nest interrupts because of the analysis complexity it incurs (how much stack do you need, for example?) and the additional overhead it requires on each interrupt. Thus I only implement it when absolutely required. The M3 port permits nested interrupts because it is easier to support them than not and the processor design is such that it does not generate an overhead.

The use of the configKERNEL_INTERRUPT_PRIORITY option will get rolled out to the other ports in time. This is not implement a complete nesting scheme as interrupts that use the FreeRTOS.org API run at the same priority - it just provides an easy way of implementing very high priority or time critical interrupts without the kernel interfering.

Full interrupt nesting is rarely actually required when using a kernel as per http://www.freertos.org/FAQISR.html#Nest (which I know you are familiar with already, I just link it here for other readers).


RE: Interrupt Nesting

Posted by John W. on October 2, 2007

Thanks for the response,

[ Back to the top ]    [ About FreeRTOS ]    [ Privacy ]    [ Sitemap ]    [ ]

Copyright (C) Amazon Web Services, Inc. or its affiliates. All rights reserved.

Latest News

NXP tweet showing LPC5500 (ARMv8-M Cortex-M33) running FreeRTOS.

Meet Richard Barry and learn about running FreeRTOS on RISC-V at FOSDEM 2019

Version 10.1.1 of the FreeRTOS kernel is available for immediate download. MIT licensed.

View a recording of the "OTA Update Security and Reliability" webinar, presented by TI and AWS.


FreeRTOS and other embedded software careers at AWS.

FreeRTOS Partners

ARM Connected RTOS partner for all ARM microcontroller cores

Espressif ESP32

IAR Partner

Microchip Premier RTOS Partner

RTOS partner of NXP for all NXP ARM microcontrollers


STMicro RTOS partner supporting ARM7, ARM Cortex-M3, ARM Cortex-M4 and ARM Cortex-M0

Texas Instruments MCU Developer Network RTOS partner for ARM and MSP430 microcontrollers

OpenRTOS and SafeRTOS

Xilinx Microblaze and Zynq partner