RISC-V RV32M1 VEGAboard Demo (RI5CY Core)
This page documents a pre-configured FreeRTOS Eclipse/GCC project that targets a RISC-V core on the RV32M1 VEGAboard. The RV32M1 incorporates a PULP RI5CY RISC-V core, a PULP Zero RISCY RISC-V core, an Arm Cortex-M4 core, and an Arm Cortex-M0+ core. At the time of writing this demo only targets the RI5CY RISC-V core.
IMPORTANT! Notes on using the FreeRTOS Pulp RI5CY RISC-V portPlease read all the following points before using this RTOS port.
- Instructions on using FreeRTOS on RISC-V cores
- Source code organisation
- The RTOS demo application functionality
- Building and running the RTOS demo application
- RTOS configuration and usage details
Instructions on using FreeRTOS on RISC-V coresIf you want to go beyond just running the demo described on this page, or if you want to create your own RISC-V FreeRTOS project, then please also read the documentation page that provides generic information on running the FreeRTOS kernel on RISC-V cores. Source Code Organization page for information on the zip file’s directory structure. The Eclipse project is located in the /Demo/RISC-V_RV32M1_Vega_GCC_Eclipse directory. More information is provided in the build instructions section below.
On RISC-V architectures the additional freertos_risc_v_chip_specific_extensions.h header file is used to extend the base RISC-V RTOS port to any chip specific extensions the target RISC-V chip may implement. The RI5CY RISC-V core used on the RV32M1 VEGAboard includes six additional additional registers over and above those defined by the base RISC-V architecture, and does not include a CLINT. Therefore this project uses the freertos_risc_v_chip_specific_extensions.h header file from the /FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM directory.
The VEGAboard RI5CY RISC-V Demo Application
FunctionalityThe constant mainCREATE_SIMPLE_BLINKY_DEMO_ONLY, which is defined at the top of main.c, is used to switch between a simple ‘blinky’ style getting started project and a more comprehensive test and demo application.
When mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1When mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 main() calls main_blinky(). main_blinky() creates a basic example that uses two tasks and one queue.
The Queue Send Task:
The queue send task is implemented by the prvQueueSendTask() function. The task sits in a loop sending the value 100 to the queue every 1000 milliseconds (1 second).
The Queue Receive Task:
The queue receive task is implemented by the prvQueueReceiveTask() function. The task sits in a loop that blocks on attempts to read from the queue (no CPU cycles are consumed while the task is blocked), writing ‘blink’ to the VEGAboard’s UART and toggling an LED each time the value 100 is received from the queue send task. As the queue send task writes to the queue every 1000 milliseconds the queue receive task unblocks and both writes to the UART and toggles the LED every 1000 milliseconds.
When mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0When mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0 main() calls main_full(). main_full() implements a comprehensive test and demo application that demonstrates and/or tests (among other things):
- Message buffers
- Stream buffers
- Task notifications
- Event groups
- Software timers
A ‘check’ task is created that periodically inspects the standard demo tasks (which contain self monitoring code) to ensure all the tasks are functioning as expected. The check task toggles the LED and outputs either a ‘.’ character or error messagto the UART each time it executes. This gives visual feedback of the system health. If the LED is toggling every 3 seconds, then the check task has not discovered any problems. If the LED is toggling every 500 milliseconds, then the check task has discovered a problem in one or more tasks, and the UART will output an error message instead of ‘.’.
To open and build the RI5CY project:
Follow the instructions
on the open-isa.org web site to install the necessary
GCC, OpenOCD and Eclipse development tools, and connect the host computer
(the computer running the development tools) to the target hardware (the VEGAboard).
Start Eclipse and either select an existing or create a new workspace
Select “Import…” from the Eclipse ‘File’ menu. The Import dialog box
In the Import dialog box, select “General->Existing Project into Workspace”.
The Import Projects dialog box will open.
Importing an existing project into the workspace
In the Import Projects dialog box, navigate to and select the
directory, and ensure the ‘copy projects into workspace’
check box is not checked.
In the ‘Projects’ window of the Import Projects dialog box, select the RTOSDemo_ri5cy project, and click finish.
Select “Build all” from the Eclipse ‘Project’ menu. The project should build
without any errors or warnings, and output a file called RTOSDemo_ri5cy.elf.
Finally, to start a debug session, right click the “RTOSDemo_ri5cy.launch”
file in the Eclipse project explorer, then select “Debug As->RTOSDemo_ri5cy”
from the pop up menu.
Selecting “Debug As->RTOSDemo_ri5cy” from the pop up windows after right clicking “RTOSDemo_ri5cy.launch”. Click to enlarge.
RTOS port specific configurationThis section relates to the information provided on the Running FreeRTOS on RISC-V Cores documentation page:
Configuration items specific to this demo are contained in FreeRTOS/Demo/RISC-V_RV32M1_Vega_GCC_Eclipse/projects/RTOSDemo_ri5cy/FreeRTOSConfig.h. The
constants defined in that file can be edited to suit your application. In particular configCLINT_BASE_ADDRESS
is set to 0 because the RI5CY core on the VEGAboard does not include a Core Local Interrupter (CLINT).
The RI5CY core has six additional registers over and above the registers
defined by the base RISC-V architecture. These registers are saved and
restored by the macros contained in the freertos_risc_v_chip_specific_extensions.h
header file located in the /FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM directory,
so that directory is in the assembler’s include path.
The interrupt handler provided in the VEGAboard’s software development kit (SDK)
is called SystemIrqHandler(), so the assembler’s command line options include
The VEGAboard includes a vectored interrupt controller. The file FreeRTOS_startup_RV32M1_ri5cy.S
is an edited version of startup_RV32M1_ri5cy.S that sets the FreeRTOS trap handler as the interrupt
handler for each vector. The FreeRTOS trap handler is called freertos_risc_v_trap_handler().
vPortEndScheduler() has not been implemented.
Source/Portable/MemMang/heap_4.c is included in the RISC-V project to provide the memory
allocation required by the RTOS kernel.
Please refer to the Memory Management section of the API documentation for
At the time of writing, the demo does not support interrupt nesting.